UPD45D128164 データシートの表示（PDF） - Elpida Memory, Inc

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UPD45D128164

128 M-bit Synchronous DRAM with Double Data Rate(4-bank, SSTL_2)

Elpida Memory, Inc 

µPD45D128442, 45D128842, 45D128164

2. Commands

Extended mode register set command

(/CS, /RAS, /CAS, /WE Low)

Fig.1 Extended mode register

set command

The µPD45D128xxx has an extended mode register that defines enabling or

disabling DLL. In this command, A0 through A11, BA0 and BA1 are the data

input pins.

After power on, the extended mode register set command must be executed to

enabling or disabling DLL.

The extended mode register can be set only when all banks are in idle state.

During tMRD, the µPD45D128xxx can not accept any other commands.

CLK

CKE H

/CS

/RAS

/CAS

/WE

BA0

BA1

A10

Add

Mode register set command

Fig.2 Mode register set command

(/CS, /RAS, /CAS, /WE Low)

The µPD45D128xxx has a mode register that defines how the device operates.

In this command, A0 through A11, BA0 and BA1 are the data input pins.

After power on, the mode register set command must be executed to initialize the

device.

The mode register can be set only when all banks are in idle state.

During tMRD, the µPD45D128xxx can not accept any other commands.

CLK

CKE H

/CS

/RAS

/CAS

/WE

BA0,BA1

A10

Add

Bank activate command

Fig.3 Bank activate command

(/CS, /RAS = Low, /CAS, /WE = High)

The µPD45D128xxx has four banks, each with 4,096 rows.

This command activates the bank and the row address selected by BA0 and

BA1, and by A0 through A11 respectively.

This command corresponds to a conventional DRAM's /RAS falling.

CLK

CKE

/CS

/RAS

/CAS

/WE

BA0,BA1

A10

Add

H

Row

Row

Data Sheet E0030N10

11

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