UPD45D128164 データシートの表示（PDF） - Elpida Memory, Inc

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UPD45D128164

128 M-bit Synchronous DRAM with Double Data Rate(4-bank, SSTL_2)

Elpida Memory, Inc 

µPD45D128442, 45D128842, 45D128164

CONTENTS

1. Input/Output Pin Function … 10

2. Commands … 11

3. Simplified State Diagram … 15

4. Truth Table … 16

4.1 Command Truth Table … 16

4.2 DM Truth Table … 16

4.3 CKE Truth Table … 16

4.4 Operative Command Table … 17

4.5 Command Truth Table for CKE … 20

5. Initialization … 21

6. Programming the Mode Register … 22

7. Mode Register … 23

7.1 Burst Length and Sequence … 24

8. Address Bits of Bank-Select and Precharge … 25

9. Precharge … 26

9.1 Read to Precharge Command Interval … 26

9.2 Write to Precharge Command Interval … 27

10. Auto Precharge … 28

10.1 Read with Auto Precharge … 28

10.2 Write with Auto Precharge … 29

11. Read/Write Command Interval … 30

11.1 Read to Read Command Interval … 30

11.2 Write to Write Command Interval … 31

11.3 Write to Read Command Interval … 32

11.4 Read to Write Command Interval … 33

8

Data Sheet E0030N10

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