SI2403 データシートの表示（PDF） - Silicon Laboratories

部品番号

コンポーネント説明

メーカー

SI2403

V.22BIS ISOMODEM® CHIPSET WITH ERROR CORRECTION

Silicon Laboratories 

Si2403

4.4. Command Mode

Upon reset, the ISOmodem® chipset is in command

mode and accepts “AT” commands. An outgoing

modem call can be made using the “ATDT#” (tone dial)

or “ATDP#” (pulse dial) command after the device is

configured. If the handshake is successful, the modem

responds with the response codes detailed in Table 12

on page 32 and enters data mode.

4.5. Data Mode

The ISOmodem chipset is in data mode while it has a

connection to another modem or is in the process of

establishing a connection.

In command and data mode, the Si2403 operates in

asynchronous DTE mode only. Data protocols are

available to provide error correction to improve reliability

(V.42 and MNP2-4).

Each connection between two modems in data mode

begins with a handshaking sequence. During that

sequence, the modems determine the line speed, data

protocol, and related parameters for the data link.

Configuration through AT commands determines the

range of choices available to the modem during the

negotiation process.

4.6. Fast Connect

The ISOmodem chipset supports a Fast Connect mode

of operation to reduce the time of a connect sequence

in originate mode. The Fast Connect modes can be

enabled for V.21, V.22, V.22bis, Bell103, and Bell212. In

addition, the Si2403 may be set to either default

asynchronous data communications equipment (DCE)

mode or a transparent HDLC synchronous mode.

4.7. Clocking/Low-Power Modes

The ISOmodem chipset contains an on-chip phase-

locked loop (PLL) and clock generator. Using either a

single crystal or master clock input, the Si2403 can

generate all the internal clocks required to support the

featured modem protocols. Either a 4.9152 MHz clock

(3.3 V max input—see Table 5 on page 8) on XTALI or a

4.9152 MHz crystal across XTALI and XTALO form the

master clock (±100 ppm max) for the Si2403. This clock

source is sent to an internal PLL that generates all

necessary internal system clocks including the DSP

clock. Figure 5 shows a block diagram of how the DSP

clock and the CLKOUT are derived.

Using the S24 S-register, the Si2403 can be set to

automatically enter sleep mode after a pre-programmed

time of inactivity with either the DTE or the remote

modem. The sleep mode is entered after (S24) seconds

have passed since the TX FIFO has been empty. The

Si2403 remains in the sleep state until either a 1 to 0

transition on TXD (serial mode) or a 1 to 0 transition on

CS (parallel mode) occurs.

Additionally, the Si2403 may be placed in a complete

Powerdown mode. Complete powerdown is

accomplished via U65[13] (PDN). Once the PDN bit is

written, the Si2403 completely powers down and can

only be powered back on via the RESET pin.

A 78.6432 MHz/(R1 + 1) clock is produced on the

CLKOUT pin that may be used as an external system

clock. R1 may be programmed via U5E to any value

between 1 and 31 (default value = 31).

To internal clocking

4.9152 MHz

CLKIN (pin 1)

78.6432 MHz

PLL

÷ (R1 + 1)

1 < R1 < 31

Figure 5. DSP and CLKOUT Generation

CLKOUT

(pin 3)

Rev. 1.2

17

Share Link: