NT3980 データシートの表示（PDF） - Novatek Microelectronics
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NT3980 Datasheet PDF : 13 Pages
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NT3980
TFT LCD Source Driver
AC Electrical Characteristics 1(Vcc =3.0V , AVDD=10V, AVSS=GND=0V, TA= -30 ~ 75℃,Tr=Tf=2ns)
Parameter
Symbol Min. Typ. Max. Unit
Conditions
CLK frequency
Fclk
-
45
70 MHz Vcc=3.0~3.6V
CLK period cycle
Tcph
14
-
-
ns
CLK pulse width
Tcw
4
-
-
ns
Data set-up time
Tsu
2
-
-
ns D00 ~ D57, REV to CLK
Data hold time
Thd
2
-
-
ns D00 ~ D57, REV to CLK
Start pulse setup time
Tss
2
--
--
ns DIO1,DIO2 to CLK
Start pulse hold time
Tsh
2
--
--
ns DIO1,DIO2 to CLK
LD high-level width
Propagation delay of DIO2/1
Tld
1
--
--
us
Tplh
6
--
12 ns CL=25pF ( Output )
Time that the last data to LD
Tldt
1
-
- Tcph
Time that LD to DIO1/2(In)
Tlds
2
-
- Tcph
POL set-up time
Tpsu
5
-
-
ns POL to LD
POL hold time
Output stable time
Tphd
5
-
-
ns POL to LD
Tst
-
4
6
us Final value precision below 30mV,
CL=150pF,R=5k ohm ,AVDD=10V
Slew rate of outputs
Tsr
3
5
- V/us 5% to 95% at 10V swing,
CL=150pF,R=5k ohm
Output loading
CL
-
-
150 pF
AC Electrical Characteristics 2(Vcc =2.5V , AVDD=10V, AVSS=GND=0V, TA= -30~75℃,Tr=Tf=3ns)
Parameter
CLK frequency
CLK period cycle
CLK pulse width
Data set-up time
Data hold time
Start pulse setup time
Start pulse hold time
LD high-level width
Propagation delay of DIO2/1
Time that the last data to LD
Time that LD to DIO1/2(In)
POL set-up time
POL hold time
Output stable time
Slew rate of outputs
Output loading
Symbol Min.
Fclk
-
Tcph
22
Tcw
7
Tsu
4
Thd
4
Tss
4
Tsh
4
Tld
1
Tplh
6
Tldt
1
Tlds
2
Tpsu
5
Tphd
5
Tst
-
Tsr
3
CL
-
Typ. Max. Unit
Conditions
35
45 MHz Vcc=2.5~3.0V
-
-
ns
-
-
ns
-
-
ns D00 ~ D57, REV to CLK
-
-
ns D00 ~ D57, REV to CLK
--
--
ns DIO1,DIO2 to CLK
--
--
ns DIO1,DIO2 to CLK
--
--
us
--
18 ns CL=25pF ( Output )
-
- Tcph
-
- Tcph
-
-
ns POL to LD
-
-
ns POL to LD
4
6
us Final value precision below 30mV,
CL=150pF,R=5k ohm ,AVDD=10V
5
- V/us 5% to 95% at 10V swing,
CL=150pF,R=5k ohm
-
150 pF
Version 1.0
11
October 16, 2001
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