ASCELL3911 データシートの表示（PDF） - austriamicrosystems AG
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ASCELL3911 Datasheet PDF : 13 Pages
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ISM 868 MHz, 433 MHz and 315 MHz FSK Transmitter – Preliminary Data Sheet
ASCell3911
Austria Mikro Systeme International AG
DATA(serial data input), D_EN (serial data enable input), D_CLK (serial data clock input)
VIH High level input voltage
VDD-0,5
-
V
VIL Low level input voltage
-
0,3
V
IIH High level input current VIH= VDD
1
µA
IIL Low level input current VIL =0 V
-1
µA
WAKEUP (µC clear output / transmitter power down input)
VOH High level output voltage IOH = -1mA
VDD-0,5
-
V
VOL Low level output voltage IOL = 1mA
-
0,3
V
VIH High level input voltage
VDD-0,5
-
V
VIL Low level input voltage
-
0,3
V
IIH High level input current VIH = VDD
1
µA
IIL Low level input current VIL =0 V; Due to
-40
µA
internal pull-up
2.4.1 µController Interface
Symbol Parameter
Conditions / Notes
Min
Tbit
FSK Data Bit duration
Twe
Time between Wake up and Data Data input prepared to
tbd
Enable
receive data
Ted
Time between Data Enable and Data input prepared to
tbd
Data
receive data
Tde
Time between Data and Data Start-up and lock PLL
tbd
Enable
Tet
Time between Data Enable and Start-up and lock PLL
tbd
Transmit
Twt
Time between Wake up and
Transmit start
Tca
Time that CLK output stays ac-
tive after Twt
VPOR
Power-On-Reset threshold volt- RESET invalid when Vdd < 1,6
age
VCCminPOR
TPOR
Power-On-Reset duration
2
VCCminPOR Minimum Supply Voltage for valid
Power-On-Reset output
Typ Max Units
tbd
s
s
s
s
s
tbd
s
tbd
s
1,8 V
10 ms
1,2 V
3 Pin Description
Note: pin ordering is preliminary - will be fixed at fab-in.
Pin Name
1 RF+
2 RF-
3 PAGND
Type
A
A
P
Description
Power amplifier output (open collector)
Power amplifier output (open collector)
Power amplifier ground
Rev. A, February 2000
Page 11 of 13
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