ASCELL3912 データシートの表示（PDF） - austriamicrosystems AG

部品番号

コンポーネント説明

メーカー

ASCELL3912

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell

austriamicrosystems AG 

ISM 868 MHz, 433 MHz and 315 MHz FSK Receiver Cell – Preliminary Data Sheet

ASCell3912

Austria Mikro Systeme International AG

TX-

SYNC

Status 13.80ms

TX-Start

DATA

12.28ms

Wake-Up

trigger

Wake up

RX

SYNC

13.80ms

DATA

12.28ms

SYNC

13.80ms

DATA

12.28ms

Receiver-sleep-time =

(STR +1) * 20 ms

start

detection

TDET0=12.28ms

TDET1=26.08ms

SYNC

13.80ms

DATA

SYNC DATA

12.28ms 13.80m

s

TX- stop

TDET2=64.44ms

Wake-Up

trigger

RX-sleep

TSTOP≤30ms

RX-

Status

XO- Receiver Wake up sequence

Set

max. 22.25ms

Data reception and store data

Data reception

XO-

Set

Interface-lines: Shown for TDET1

µC_CLK

WAKE_UP

RE_INT

Internal flags: Shown for TDET1

RX

DR

TBWI ≤0.5ms

TINT = 0.5ms

TCAI = 16/FCLK

data detection

completed

shown for TDET1

µC-readout

Figure 2:

r Detection with 0 GSM-interferer

TDET0=12.28ms

r Detection with 1 GSM interferer or in 50% Duty Cycle ModeTDET1=26.08ms

r Detection with 2 GSM interferer

TDET2=64.44ms

r Active time after last useful data

TSTOP ≤30ms

r Cristal Oscillator setup-time

TXOS =5ms

ASCell3912 basic timing.

Note: The Interface timing and the timing of the internal flags are shown in Figure 2 for a detection time of TDET1.

1.2.3 Receiver Configuration

The configuration register can be loaded from a µC via the serial interface. The Table 2 below

shows the contents of the configuration register. Bit b0 is the first transmitted bit. The setup

contains the LNA set, frequency band and the sleep time interval of the receiver.

bit #

0

[1..2]

[3..8]

Name

LNA

FB[1:0]

STR[5:0]

Description

Configuration

LNA gain switch

L= LNA Gain is high

H= LNA Gain is -10dB

Frequency band select with L, L (FB1, FB0) = 868.3 MHz

FB1 is MSB

L, H = 433.92 MHz

H, L = 315 MHz

H, H = not used

Sleep time interval set of

the receiver, with STR5 is

MSB

tsleep = (STR + 1) * 20ms

Comments

default

default

Note: for STR = 00h the

witing period between

two consecutive wake-

up cycles will be 148 bit.

Table 2: Format of the configuration Register

Rev. A, February 2000

Page 6 of 14

Share Link: