NJU3430 データシートの表示（PDF） - Japan Radio Corporation

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NJU3430

16-CHARACTER 1-LINE DOT MATRIX VFD CONTROLLER DRIVER16-CHARACTER 1-LINE DOT MATRIX VFD CONTROLLER DRIVER

Japan Radio Corporation  

n PIN CONFIGURATION

NJU3430

V SS

O SC 1

O SC 2

R ST

CS

CLK

SI

RS

V DD

P1

M K2

M K1

S1

S2

S3

S4

48

49

33

32

T1

S 35

S 34

S 33

S 32

S 31

S 30

S 29

NJU 3430

S 28

S 27

S 26

S 25

S 24

S 23

S 22

64

17

S 21

1

16

n BLOCK DIAGRAM

RST

SI

CS

CLK

RS

RESET

8bits

Shift

Reg.

Instruction

Decoder

Line

Address

Counter

Timing

Gen.

OSC1

OSC2

VDD

VSS

VFDP

CR

OSC.

State

Reg.

Display

Control

Address

Selector

Read

Address

Counter

MK RAM

16x2bit

CG RAM

35x8bit

CG ROM

8,400bit

DD RAM

16x8bit

Icon

Driver

MK1∼MK2

Segment

Driver

Port

Driver

S1∼S35

P1

Timing

Driver

T1∼T16

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