AD1933 データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD1933 Datasheet PDF : 28 Pages
| |||
AD1933
Data Sheet
TIMING SPECIFICATIONS
−40°C < TC < +125°C, DVDD = 3.3 V ± 10%.
Table 7.
Parameter
INPUT MASTER CLOCK (MCLK) AND RESET
tMH
tMH
fMCLK
fMCLK
tPDR
tPDRR
PLL
Lock Time
256 fS VCO Clock, Output Duty Cycle
MCLKO/XO Pin
SPI PORT
tCCH
tCCL
fCCLK
tCDS
tCDH
tCLS
tCLH
tCLHIGH
tCOE
tCOD
tCOH
tCOTS
DAC SERIAL PORT
tDBH
tDBL
tDLS
tDLH
tDLS
tDDS
tDDH
AUXTDM SERIAL PORT
tABH
tABL
tALS
tALH
tALS
tDDS
tDDH
AUXILIARY INTERFACE
tDXDD
tXBH
tXBL
tDLS
tDLH
Condition
Comments
Min Max Unit
MCLK duty cycle
MCLK frequency
RST low
RST recovery
DAC clock source = PLL clock @ 256 fS, 384 fS,
512 fS, and 768 fS
DAC clock source = direct MCLK @ 512 fS
(bypass on-chip PLL)
PLL mode, 256 fS reference
Direct 512 fS mode
Reset to active output
40 60 %
40 60 %
6.9 13.8 MHz
27.6 MHz
15
ns
4096
tMCLK
MCLK and LR clock input
10 ms
40 60 %
CCLK high
CCLK low
CCLK frequency
CIN setup
CIN hold
CLATCH setup
CLATCH hold
CLATCH high
COUT enable
COUT delay
COUT hold
COUT tristate
DBCLK high
DBCLK low
DLRCLK setup
DLRCLK hold
DLRCLK skew
DSDATA setup
DSDATA hold
AUXTDMBCLK high
AUXTDMBCLK low
AUXTDMLRCLK setup
AUXTDMLRCLK hold
AUXTDMLRCLK skew
DSDATA setup
DSDATA hold
See Figure 9
35
ns
35
ns
fCCLK = 1/tCCP, only tCCP shown in Figure 9
10 MHz
To CCLK rising
10
ns
From CCLK rising
10
ns
To CCLK rising
10
ns
From CCLK rising
10
ns
Not shown in Figure 9
10
ns
From CCLK falling
30 ns
From CCLK falling
30 ns
From CCLK falling, not shown in Figure 9
30
ns
From CCLK falling
30 ns
See Figure 16
Slave mode
10
ns
Slave mode
10
ns
To DBCLK rising, slave mode
10
ns
From DBCLK rising, slave mode
5
ns
From DBCLK falling, master mode
−8 +8 ns
To DBCLK rising
10
ns
From DBCLK rising
5
ns
See Figure 17
Slave mode
10
ns
Slave mode
10
ns
To AUXTDMBCLK rising, slave mode
10
ns
From AUXTDMBCLK rising, slave mode
5
ns
From AUXTDMBCLK falling, master mode
−8 +8 ns
To AUXTDMBCLK, not shown in Figure 17
10
ns
From AUXTDMBCLK rising, not shown in Figure 17 5
ns
AUXDATA delay
AUXBCLK high
AUXBCLK low
AUXLRCLK setup
AUXLRCLK hold
From AUXBCLK falling
To AUXBCLK rising
From AUXBCLK rising
18 ns
10
ns
10
ns
10
ns
5
ns
Rev. E | Page 6 of 28
Share Link: 