AT32UC3L0128-ZAUR データシートの表示（PDF） - Atmel Corporation
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AT32UC3L0128-ZAUR Datasheet PDF : 852 Pages
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Figure 4-1. Overview of the AVR32UC CPU
AT32UC3L0128/256
OCD
system
Power/
Reset
control
AVR32UC CPU pipeline
MPU
Instruction memory controller
High Speed Bus master
Data memory controller
High Speed
Bus master
High
Speed
Bus slave
CPU Local
Bus
master
CPU RAM
4.3.1
Pipeline Overview
AVR32UC has three pipeline stages, Instruction Fetch (IF), Instruction Decode (ID), and Instruc-
tion Execute (EX). The EX stage is split into three parallel subsections, one arithmetic/logic
(ALU) section, one multiply (MUL) section, and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 4-2 on page 21 shows an overview of the AVR32UC pipeline stages.
20
32145C–06/2013
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