AT93C56A(2006) データシートの表示（PDF） - Atmel Corporation

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AT93C56A
(Rev.:2006)

Three-wire Serial EEPROM

Atmel Corporation 

AT93C56A/66A

Table 5. Instruction Set for the AT93C56A and AT93C66A

Op

Instruction SB Code

Address

x8

x 16

READ

1

10

A8 – A0

A7 – A0

Data

x8

x 16

EWEN

ERASE

WRITE

ERAL

1

00

11XXXXXXX 11XXXXXX

1

11

1

01

A8 – A0

A8 – A0

A7 – A0

A7 – A0

D7 – D0

D15 – D0

1

00

10XXXXXXX 10XXXXXX

WRAL

1

00

01XXXXXXX 01XXXXXX D7 – D0

D15 – D0

EWDS

1

00

00XXXXXXX 00XXXXXX

Note: The X’s in the address field represent don’t care values and must be clocked.

Comments

Reads data stored in memory, at

specified address.

Write enable must precede all

programming modes.

Erases memory location An – A0.

Writes memory location An – A0.

Erases all memory locations. Valid

only at VCC = 4.5V to 5.5V.

Writes all memory locations. Valid

only at VCC = 5.0V ±10% and Disable

Register cleared.

Disables all programming

instructions.

Functional Description

The AT93C56A/66A is accessed via a simple and versatile three-wire serial communi-

cation interface. Device operation is controlled by seven instructions issued by the host

processor. A valid instruction starts with a rising edge of CS and consists of a Start

Bit (logic “1”) followed by the appropriate Op Code and the desired memory address

location.

READ (READ): The Read (READ) instruction contains the address code for the mem-

ory location to be read. After the instruction and address are decoded, data from the

selected memory location is available at the serial output pin DO. Output data changes

are synchronized with the rising edges of serial clock SK. It should be noted that a

dummy bit (logic “0”) precedes the 8- or 16-bit data output string. The AT93C56A/66A

supports sequential read operations. The device will automatically increment the inter-

nal address pointer and clock out the next memory location as long as Chip Select (CS)

is held high. In this case, the dummy bit (logic “0”) will not be clocked out between mem-

ory locations, thus allowing for a continuous stream of data to be read.

ERASE/WRITE (EWEN): To assure data integrity, the part automatically goes into the

Erase/Write Disable (EWDS) state when power is first applied. An Erase/Write Enable

(EWEN) instruction must be executed first before any programming instructions can be

carried out. Please note that once in the EWEN state, programming remains enabled

until an EWDS instruction is executed or VCC power is removed from the part.

ERASE (ERASE): The Erase instruction programs all bits in the specified memory loca-

tion to the logical “1” state. The self-timed erase cycle starts once the ERASE instruction

and address are decoded. The DO pin outputs the Ready/Busy status of the part if CS is

brought high after being kept low for a minimum of 250 ns (tCS). A logic “1” at pin DO

indicates that the selected memory location has been erased, and the part is ready for

another instruction.

5

3378K–SEEPR–12/06

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