DS1307ZN データシートの表示（PDF） - Dallas Semiconductor -> Maxim Integrated
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DS1307ZN Datasheet PDF : 12 Pages
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AC ELECTRICAL CHARACTERISTICS
PARAMETER
SCL Clock Frequency
Bus Free Time Between a STOP and
START Condition
Hold Time (Repeated) START Condition
LOW Period of SCL Clock
HIGH Period of SCL Clock
Set-up Time for a Repeated START
Condition
Data Hold Time
Data Set-up Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-up Time for STOP Condition
Capacitive Load for each Bus Line
I/O Capacitance (TA = 25ºC)
Crystal Specified Load Capacitance
(TA = 25ºC)
*Unless otherwise specified.
SYMBOL
fSCL
tBUF
tHD:STA
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
CB
CI/O
MIN
0
4.7
4.0
4.7
4.0
4.7
0
250
4.7
DS1307
(Over the operating range*)
TYP MAX UNITS NOTES
100
kHz
ms
ms
3
ms
ms
ms
ms
4,5
ns
1000
ns
300
ns
ms
400
pF
6
10
pF
12.5
pF
NOTES:
1. ICCS specified with VCC = 5.0V and SDA, SCL = 5.0V.
2. VCC = 0V, VBAT = 3V.
3. After this period, the first clock pulse is generated.
4. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the
VIHMIN of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
5. The maximum tHD:DAT has only to be met if the device does not stretch the LOW period (tLOW) of the
SCL signal.
6. CB – Total capacitance of one bus line in pF.
7. ICCA – SCL clocking at max frequency = 100kHz.
8. VPF measured at VBAT = 3.0V.
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