ADT7476AARQZ-R データシートの表示（PDF） - ON Semiconductor
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ADT7476AARQZ-R Datasheet PDF : 69 Pages
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ADT7476A
Table 3. ELECTRICAL CHARACTERISTICS (continued)
(TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted) (Note 1)
Parameter
Conditions
Min
Typ
Max
Unit
Fan RPM-to-Digital Converter
Accuracy
Full-Scale Count
0°C ≤ TA ≤ 70°C
−40°C ≤ TA ≤ +120°C
−
−
±6
%
−
−
±10
−
−
65,535
Nominal Input RPM
Fan Count = 0xBFFF
Fan Count = 0x3FFF
Fan Count = 0x0438
Fan Count = 0x021C
−
109
−
RPM
−
329
−
−
5,000
−
−
10,000
−
Open-Drain Digital Outputs, PWM1 TO PWM3, XTO
Current Sink, IOL
Output Low Voltage, VOL
IOUT = −8.0 mA
High Level Output Current, IOH
VOUT = VCC
Open-Drain Serial Data Bus Output (SDA)
−
−
8.0
mA
−
−
0.4
V
−
0.1
20
mA
Output Low Voltage, VOL
IOUT = −4.0 mA
High Level Output Current, IOH
VOUT = VCC
SMBus Digital Inputs (SCL, SDA) (Note 2)
−
−
0.4
V
−
0.1
1.0
mA
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
2.0
−
−
V
−
−
0.8
V
−
500
−
mV
Digital Input Logic Levels (TACH Inputs)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
Maximum Input Voltage
Minimum Input Voltage
2.0
−
5.5
V
−0.3
−
0.8
V
−
0.5
−
V p-p
Digital Input Logic Levels (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
Digital Input Current
0.75 × VCCP
−
−
V
−
−
0.8
V
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
Serial Bus Timing (See Figure 2)
VIN = VCC
VIN = 0
−
±1
−
mA
−
±1
−
mA
−
5.0
−
pF
Clock Frequency, fSCLK
10
−
400
kHz
Glitch Immunity, tSW
@ 100 kHz
−
−
50
ns
Bus Free Time, tBUF
@ 100 kHz
4.7
−
−
ms
SCL Low Time, tLOW
@ 100 kHz
4.7
−
−
ms
SCL High Time, tHIGH
@ 100 kHz
4.0
−
50
ms
SCL, SDA Rise Time, tr
@ 100 kHz
−
−
1,000
ns
SCL, SDA Fall Time, tf
@ 100 kHz
−
−
300
ms
Data Setup Time, tSU;DAT
@ 100 kHz
250
−
−
ns
Detect Clock Low Timeout, tTIMEOUT
Can be Optionally Disabled
15
−
35
ms
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. All voltages are measured with respect to GND, unless otherwise specified. Typical voltages are TA = 25°C and represent a parametric norm.
Logic inputs accept input high voltages up to VMAX, even when the device is operating down to VMIN. Timing specifications are tested at logic
levels of VIL = 0.8 V for a falling edge, and VIH = 2.0 V for a rising edge.
2. SMBus timing specifications are guaranteed by design and are not production tested.
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