UPD78064A データシートの表示（PDF） - NEC => Renesas Technology

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UPD78064A

8-BIT SINGLE-CHIP MICROCONTROLLER

NEC => Renesas Technology 

DATA SHEET

MOS INTEGRATED CIRCUIT

µPD78062(A), 78063(A), 78064(A)

8-BIT SINGLE-CHIP MICROCONTROLLER

DESCRIPTION

The µPD78062(A), 78063(A), and 78064(A) are products to which a quality assurance program more stringent than that

used for the µPD78062, 78063, and 78064 (standard models) is applied (NEC classifies these products as “special” quality

grade models).

µPD78062(A), 78063(A), and 78064(A) are products in the µPD78064 subseries within the 78K/0 series, which

incorporate LCD controller/driver, 8-bit resolution A/D converter, timer, serial interface, interrupt functions and many other

peripheral hardwares.

Various development tools are also provided.

For the details of functional description, refer to the following user's manual.Be sure to read this manual

before designing your system.

µPD78064 78064Y Subseries User's Manual : U10105E

78K/0 Series User's Manual (Instruction : IEU-1372

FEATURES

• Large on-chip ROM & RAM

Item

Product Name

µPD78062(A)

µPD78063(A)

µPD78064(A)

Program Memory

(ROM)

16K bytes

24K bytes

32K bytes

Data Memory

Internal High-Speed RAM LCD Display RAM

512 bytes

1024 bytes

40 × 4 bits

Package

100-pin plastic QFP (fine pitch)

(14 × 14mm, 0.5 mm pitch)

100-pin plastic QFP

(14 × 20 mm, 0.65 mm pitch)

100-pin plastic LQFPNote (fine pitch)

(14 × 14 mm, 0.5 mm pitch)

Note Under planning

• Minimum instruction execution time can be varied from high speed (0.4 µs) to ultra-low speed (122 µs)

• I/O ports: 57 (including segment signal output dual-function pins)

• LCD controller/driver

Supply voltage

VDD = 2.0 to 6.0 V (Static display mode)

VDD = 2.5 to 6.0 V (1/3 bias)

VDD = 2.7 to 6.0 V (1/2 bias)

• 8-bit resolution A /D converter : 8 channels

• Serial interface : 2 channels

• Timer: 5 channels

• Supply voltage : VDD = 2.0 to 6.0 V

The information in this document is subject to change without notice.

Document No. U10335EJ2V0DS00 (2nd edition)

Date Published August 1997 N

The mark shows major revised points.

Printed in Japan

©

1997

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