UPB1505GR-E1 データシートの表示（PDF） - NEC => Renesas Technology
部品番号
コンポーネント説明
メーカー
UPB1505GR-E1 Datasheet PDF : 8 Pages
| |||
µPB1505GR
SELECTOR GUIDE
FEATURES
2.5 GHz / ÷512, ÷256
2.5 GHz / ÷128, ÷64
3.0 GHz / ÷256, ÷128, ÷64
PRODUCT
NUMBER
µPB586G
µPB588G
µPB1505GR
ICC
(mA)
28
26
14
fin
(GHz)
VCC
(V)
PACKAGE
0.5 to 2.5
5
8 pin SOP
0.5 to 2.5
5
8 pin SOP
0.5 to 3.0
5
8 pin SOP
Notice Typical performance. Please refer to Electrical Characteristics in detail.
To know the associated products, please refer to their latest data sheets.
PIN ASSIGNMENT
NEC original
Typical of prescaler
INTERNAL BLOCK DIAGRAM
VCC
2
INPUT 1
BYPASS 8
1 / 64
1/2
1/2
Buff.
4 OUTPUT
5, 7
GND
PIN DESCRIPTIONS
3
SW1
6
SW2
PIN NO.
1
SYMBOL
IN
ASSIGNMENT
Frequency input
pin
2
VCC
Power supply pin
3
SW1
Divided ratio
control input pin 1
6
SW2
Divided ratio
control input pin 2
FUNCTIONS AND EXPLANATION
Input frequency from an external VCO output.
Must be coupled with capacitor (e.g. 1 000 pF) for DC cut.
Supply voltage 5.0±0.5 V for operation. Must be connected bypass capacitor
(e.g. 1 000 pF) to minimize ground impedance.
Divided ratio control can be governed by following input data to these pins.
H
SW1
L
SW2
H
L
1/64
1/128
1/128
1/256
4
OUT
Divided frequency This frequency output can be interfaced to CMOS PLL.
output pin
Must be coupled with capacitor (e.g. 1 000 pF) for DC cut.
5
GND
Ground pin
7
This pin must be connected to the system ground with minimum inductance.
Ground pattern on the board should be formed as wide as possible.
(Track length should be kept as short as possible.)
8
IN
Frequency-input
This pin must be connected bypass capacitor (e.g. 1 000 pF) to minimize ground
bypass pin
impedance.
2
Data Sheet P10872EJ3V0DS00
Share Link: 