Q67100-Q1101 データシートの表示（PDF） - Infineon Technologies

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Q67100-Q1101

4M × 4-Bit Dynamic RAM 2k & 4k Refresh (Hyper Page Mode - EDO)

Infineon Technologies 

HYB 5116(7)405BJ-50/-60

HYB 3116(7)405BJ/BT(L)-50/-60

4M × 4 EDO-DRAM

DC Characteristics (cont’d)

TA = 0 to 70 °C, VSS = 0 V, tT = 2 ns

Parameter

Symbol

Limit Values

min.

max.

2k 4k

Common Parameters

Input leakage current

II(L)

(0 V ≤ VIH ≤ VCC + 0.3 V, all other pins = 0 V)

Output leakage current

IO(L)

(DO is disabled, 0 V ≤ VOUT ≤ VCC + 0.3 V)

Average VCC supply current

ICC1

-50 version

-60 version

(RAS, CAS, address cycling: tRC = tRC MIN.)

Standby VCC supply current

ICC2

(RAS = CAS = VIH)

Average VCC supply current, during RAS-only ICC3

refresh cycles

-50 version

-60 version

(RAS cycling, CAS = VIH, tRC = tRC MIN.)

Average VCC supply current,during hyper page ICC4

mode (EDO)

-50 version

-60 version

(RAS = VIL, CAS, address cycling:

tPC = tPC MIN.)

Standby VCC supply current

ICC5

(RAS = CAS = VCC – 0.2 V)

Average VCC supply current, during CAS-

ICC6

before-RAS refresh mode

-50 version

-60 version

(RAS, CAS cycling: tRC = tRC MIN.)

Average Self Refresh current

ICC7

(CBR cycle with tRAS > tRASS MIN., CAS held

low, WE = VCC – 0.2 V, Address and

Din = VCC – 0.2 V or 0.2 V)

– 10

10

– 10

10

–

80 50

–

70 40

–

2

–

80 50

–

70 40

–

35

–

30

–

1

200

–

80 50

–

70 40

–

250

Unit Notes

µA 1

µA 1

mA 2, 3, 4

mA 2, 3, 4

mA –

mA 2, 4

mA 2, 4

mA 2, 3, 4

mA 2, 3, 4

mA 1

µA L-version

mA 2, 4

mA 2, 4

µA L-

version

only

Semiconductor Group

7

1998-10-01

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