IN24LC04B データシートの表示（PDF） - IK Semicon Co., Ltd
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IN24LC04B Datasheet PDF : 10 Pages
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IN24LC04B/08B
ACKNOWLEDGE POLLING
Since the device will not acknowledge during a write cycle, this can be used to determine when the
cycle is complete (this feature can be used to maximize bus throughput). Once
the stop condition for a write command has been
issued from the master, the device initiates the
Figure 7. Acknowledge Polling Flow
internally timed write cycle, ACK polling can be
initiated immediately. This involves the master
sending a start condition followed by the control
byte for a write command (R/W =0). If the
device is still busy with the write cycle, then no
ACK will be returned. If the cycle is complete,
then the device will return the ACK and the
master can then proceed with the next read or
write command. See Figure 7 for flow diagram.
WRITE PROTECTION
The IN24LC04B/08B can be used as a serial
ROM when the WP pin is connected to Vcc.
Programming will be inhibited and the entire
memory will be write-protected.
READ OPERATION
Read operations are initiated in the same way as
write operations with the exception that the R/W
bit of the slave address is set to one. There are
three basic types of read operations: current
address read, random read, and sequential read.
Current Address Read
The IN24LC04B/08B contains an address counter that maintains the address of the last word
accessed, internally incremented by one. Therefore, if the previous access (either a read or write
operation) was to address n, the next current address read operation would access data from address
n + 1. Upon receipt of the slave address with R/W bit set to one, the IN24LC04B/08B issues an
acknowledge and transmits the eight bit data word. The master will not acknowledge the transfer
but does generate a stop condition and the IN24LC04/08 discontinues transmission (see Figure 9).
Random Read
Random read operations allow the master to access any memory location in a random manner. To
perform this type of read operation, first the word address must be set. This is done by sending the
word address to the IN24LC04B/08B as part of a write operation. After the word address is sent,
the master generates a start condition following the acknowledge. This terminates the write
operation, but not before the internal address pointer is set. Then the master issues the control byte
again but with the R/W bit set to a one. The IN24LC04B/08B will then issue an acknowledge and
transmits the eight bit data word. The master will not acknowledge the transfer but does generate a
stop condition and the IN24LC04B/08B discontinues transmission (see Figure 10).
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