MC13193 データシートの表示（PDF） - Freescale Semiconductor
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MC13193 Datasheet PDF : 24 Pages
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Data Transfer Modes
4.2 Receive Path Description
In the receive signal path, the RF input is converted to low IF In-phase and Quadrature (I & Q) signals
through two down-conversion stages. A Clear Channel Assessment (CCA) can be performed based upon
the baseband energy integrated over a specific time interval. The digital back end performs Differential
Chip Detection (DCD), the correlator “de-spreads” the Direct Sequence Spread Spectrum (DSSS) Offset
QPSK (O-QPSK) signal, determines the symbols and packets, and detects the data.
The preamble, SFD, and FLI are parsed and used to detect the payload data and FCS which are stored in
RAM. A two-byte FCS is calculated on the received data and compared to the FCS value appended to the
transmitted data, which generates a Cyclical Redundancy Check (CRC) result. Link Quality is measured
over a 64 µs period after the packet preamble and stored in RAM.
If the MC13192/MC13193 is in packet mode, the data is processed as an entire packet. The MCU is
notified that an entire packet has been received via an interrupt.
If the MC13192/MC13193 is in streaming mode, the MCU is notified by an interrupt on a word-by-word
basis.
Figure 1 shows CCA reported power level versus input power. Note that CCA reported power saturates at
about -57 dBm input power which is well above IEEE 802.15.4 Standard requirements. Figure 2 shows
energy detection/LQI reported level versus input power. Note that for both graphs the required IEEE
802.15.4 Standard accuracy and range limits are shown.
-50
-60
-70
802.15.4 Accuracy
and range Requirements
-80
-90
-100
-90
-80
-70
-60
-50
Input Pow er (dBm)
Figure 1. Reported Power Level versus Input Power in Clear Channel Assessment Mode
MC13192/MC13193 Technical Data, Rev. 2.9
4
Freescale Semiconductor
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