MC13193 データシートの表示（PDF） - Freescale Semiconductor
部品番号
コンポーネント説明
メーカー
MC13193 Datasheet PDF : 24 Pages
| |||
Data Transfer Modes
4.3 Transmit Path Description
For the transmit path, the TX data that was previously stored in RAM is retrieved (packet mode) or the TX
data is clocked in via the SPI (stream mode), formed into packets per the 802.15.4 PHY, spread, and then
up-converted to the transmit frequency.
If the MC13192/MC13193 is in packet mode, data is processed as an entire packet. The data is first loaded
into the TX buffer. The MCU then requests that the MC13192/MC13193 transmit the data. The MCU is
notified via an interrupt when the whole packet has successfully been transmitted.
In streaming mode, the data is fed to the MC13192/MC13193 on a word-by-word basis with an interrupt
serving as a notification that the MC13192/MC13193 is ready for more data. This continues until the
whole packet is transmitted.
R F IN +
R F IN -
V DDLO 2
XTAL1
XTAL2
VDDLO1
PAO+
PAO-
1s t IF M ix er
LN A IF = 65 M Hz
2nd IF M ix er
IF = 1 M Hz P M A
Dec im ation B as eband M atc hed
F ilter
M ix er
F ilter
CCA
DC D
Packet
P roc es s or
Pow er-U p
C ontrol
Logic
÷4
256 M Hz
Cry s tal
O s c illator
16 M Hz
PA
P has e S hift M odulator
AGC
Program m able
Presc aler
R eceiv e
Packet RAM
R ec eiv e R AM
A rbiter
24 Bit Ev ent T im er
Sequence
M anager
(C ontrol Logic )
4 Program m able
T im er C om parators
S y nth esize r
2.45 GHz
V CO
T ransm it
Packet RAM 2
T ransm it
Packet RAM 1
T ransm it R AM
A rbiter
Sy m bol
G eneration
FCS
G eneration
Header
G eneration
A n a lo g
R egulator
D ig ita l
R egulator L
D ig ita l
R egulator H
C ry s tal
R egulator
VCO
R egulator
IR Q
A rbiter
Figure 3. MC13192 Simplified Block Diagram
VDDA
VBATT
V DDIN T
VDDD
VDDVC O
RXTXEN
CE
M OSI
M IS O
S P IC LK
ATTN
RST
G P IO 1
G P IO 2
G P IO 3
G P IO 4
G P IO 5
G P IO 6
G P IO 7
IR Q
C LKO
MC13192/MC13193 Technical Data, Rev. 2.9
6
Freescale Semiconductor
Share Link: 