M2S56D40ATP-75L データシートの表示（PDF） - MITSUBISHI ELECTRIC

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M2S56D40ATP-75L

256M Double Data Rate Synchronous DRAM

MITSUBISHI ELECTRIC  

DDR SDRAM (Rev.1.0)

Jul. '01 Preliminary

BLOCK DIAGRAM

DLL

MITSUBISHI LSIs

M2S56D20/ 30/ 40AKT

256M Double Data Rate Synchronous DRAM

DQ0 - 15

UDQS,LDQS

I/O Buffer

QS Buffer

Memory

Array

Bank #0

Memory

Array

Bank #1

Memory

Array

Bank #2

Memory

Array

Bank #3

Mode Register

Control Circuitry

Address Buffer

A0-12 BA0,1

Clock Buffer

Control Signal Buffer

/CS /RAS /CAS /WE UDM,

CLK /CLK CKE

LDM

Type Designation Code

This rule is applied to only Synchronous DRAM family.

M 2 S 56 D 3 0 A TP –75A

Speed Grade 10: 125MHz@CL=2.5,100MHz@CL=2.0

75: 133MHz@CL=2.5,100MHz@CL=2.0

75A: 133MHz@CL=2.5,133MHz@CL=2.0

Package Type TP: TSOP(II)

Process Generation

Function Reserved for Future Use

Organization 2 n 2: x4, 3: x8, 4: x16

D DR Synchronous DRAM

Density 56: 256M bits

Interface V:LVTTL, S:SSTL_3, _2

Memory Style (DRAM)

Mitsubishi Main Designation

MITSUBISHI ELECTRIC

4

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