AD7450ARMZ データシートの表示（PDF） - Analog Devices
部品番号
コンポーネント説明
メーカー
AD7450ARMZ Datasheet PDF : 22 Pages
| |||
AD7450
TIMING SPECIFICATIONS1, 2
(VDD = 2.7 V to 3.3 V, fSCLK = 15 MHz, fS = 833 kSPS, VREF = 1.25 V; VDD = 4.75 V to 5.25 V,
fSCLK = 18 MHz, fS = 1 MSPS, VREF = 2.5 V; VCM3 = VREF; TA = TMIN to TMAX, unless otherwise noted.)
Parameter
fSCLK4
tCONVERT
tQUIET
Limit at TMIN, TMAX
3V
5V
50
15
16 ϫ tSCLK
1.07
25
50
18
16 ϫ tSCLK
0.88
25
t1
t2
t35
t45
t5
t6
t7
t86
tPOWER-UP7
10
10
20
40
0.4 tSCLK
0.4 tSCLK
10
10
35
1
10
10
20
40
0.4 tSCLK
0.4 tSCLK
10
10
35
1
Unit
kHz min
MHz max
µs max
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
ns min
ns max
µs max
Description
tSCLK = 1/fSCLK
SCLK = 15 MHz, 18 MHz
Minimum Quiet Time between the End of a Serial Read and the Next
Falling Edge of CS
Minimum CS Pulsewidth
CS Falling Edge to SCLK Falling Edge Setup Time
Delay from CS Falling Edge until SDATA Three-State Disabled
Data Access Time after SCLK Falling Edge
SCLK High Pulsewidth
SCLK Low Pulsewidth
SCLK Edge to Data Valid Hold Time
SCLK Falling Edge to SDATA Three-State Enabled
SCLK Falling Edge to SDATA Three-State Enabled
Power-Up Time from Full Power-Down
NOTES
1Sample tested at 25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of 1.6 V.
2See Figure 1 and the Serial Interface section.
3Common-mode voltage.
4Mark/space ratio for the SCLK input is 40/60 to 60/40.
5Measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V with VDD = 5 V, and the time for an output to cross
0.4 V or 2.0 V for VDD = 3 V.
6t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t 8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
7See Power-Up Time section.
Specifications subject to change without notice.
t1
CS
SCLK
SDATA
t2
1
2
t3
0
0
0
4 LEADING ZEROS
tCONVERT
t5
3
4
5
t7
t4
0
DB11
DB10
13
14
15
16
t6
t8
tQUIET
DB2
DB1
DB0
THREE-STATE
Figure 1. Serial Interface Timing Diagram
–4–
Rev. A
Share Link: 