MK2732-06GTR データシートの表示（PDF） - Integrated Circuit Systems
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MK2732-06GTR Datasheet PDF : 4 Pages
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PRELIMINARY INFORMATION
MK2732-06
Low Phase Noise VCXO+Multiplier
Pin Assignment
MK2732-06
X1 1
VDD5 2
VDD5 3
VIN 4
GND 5
GND 6
S1 7
OE 8
16 X2
15 REFCLK
14 NC
13 GND
12 CLK2
11 VDDIO
10 S0
9 CLK1
16 pin (173 mil) TSSOP
Clock Select Table
S1 S0 Input
CLK1
0 0 13.248 52.992
0 M 13.248 13.248
0 1 13.248 13.248
M 0 13.248 52.992
M M 13.5
54
M1
13.5
54
10
13.5
27
1 M Test mode
-
11
13.5
27
0=connect directly to GND
M=leave unconnected (floating)
1=connect directly to VDDIO
off=output stopped low.
CLK2
35.328
35.328
35.328
35.328
27
27
54
-
27
Refclk
off
off
on
on
off
on
on
-
on
Pin Descriptions
Number
1
2, 3
4
5, 6, 13
7
8
9
10
11
12
14
15
16
Name
X1
VDD5
VIN
GND
S1
OE
CLK1
S0
VDDIO
CLK2
NC
REFCLK
X2
Type
XI
P
VI
P
TI
I
O
TI
P
O
-
O
XO
Description
Crystal connection. Connect to a pullable crystal of 10-14.318 MHz.
Core VDD. Connect to +5V.
Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO.
Connect to ground.
Select input #1. Selects outputs per table above. Do not exceed VDDIO.
Output Enable. Tri-states outputs when low. Do not exceed VDDIO.
Clock Output #1 per table above. Amplitude = VDDIO.
Select input #0. Selects outputs per table above. Do not exceed VDDIO.
Input and output VDD. Connect to +3.3V or +5V. Clock amplitude matches this voltage.
Clock Output #2 per table above. Amplitude = VDDIO.
Nothing is connected internally to this pin.
Buffered crystal VCXO clock
Crystal connection. Connect to a pullable crystal of 10-14 MHz.
Key: I = Input; TI = tri-level input; O = output; P = power supply connection; VI = analog voltage input;
XI, XO = crystal pins.
External Components
The MK2732-06 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between VDD5 and GND on pins 3 and 5, and VDDIO and
GND on pins 11 and 13, as close to the MK2732-06 as possible. A series termination resistor of 33 Ω may
be used for each clock output. The input crystal must be connected as close to the chip as possible. The
input crystal should be a fundamental mode, parallel resonant, pullable, AT cut. A crystal with 14 pF load
capacitance is recommended. Consult ICS/MicroClock for recommended suppliers. IMPORTANT -
consult the application note MAN05 for layout guidelines.
MDS 2732-06 C
2
Revision 120600
Printed 12/21/00
Integrated Circuit Systems • 525 Race Street • San Jose • CA •95126 •(408) 295-9800tel•www.icst.com
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