PLCD5580 データシートの表示（PDF） - Infineon Technologies

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PLCD5580

Low Power 0.145” 8-Character, 5x5 Dot Matrix Parallel Input Alphanumeric Intelligent Display™

Infineon Technologies 

Top View

28

15

1

Pin Assignment

Pin

Function

Pin

1

RST

28

2

FL

27

3

A0

26

4

A1

25

5

A2

24

6

A3

23

7

Substr. bias

22

8

Substr. bias

21

9

Substr. bias

20

10

No Connect

19

11

CLKSEL

18

12

CLK I/O

17

13

WR

16

14

VCC

15

14

Function

D7

D6

D5

D4

D3

D2

No Pin

No Pin

D1

D0

No Connect

CE

GND (logic)

GND (supply)

TOP VIEW

Pin Function

1 RST

2 FL

3 A0

4 A1

5 A2

6 A3

7 Substr. bias

8 Substr. bias

9 Substr. bias

10 No connect

11 CLKSEL

12 CLK I/O

13 WR

14 VCC

15 GND

16 GND

17 CE

18 No connect

19 D0

20 D1

21 No pin

22 No pin

23 D2

24 D3

25 D4

26 D5

27 D6

28 D7

Definition

Used to initialize a display and synchro-

nize blinking for multiple displays

Low input accesses the Flash RAM

Address input LSB

Address input

Address input MSB

Mode selector

Optional connection to VCC. Can’t be

used to supply power to display.

See Definition 7

See Definition 7

Selects internal/external clock source

Outputs master clock or inputs external

clock

A low will write data into the display if CE

is low

Positive power supply input

Analog Ground for LED drivers

Digital Ground for internal drivers

Enables access to the display

Data input LSB

Data input

Data input

Data input

Data input

Data input

Data input

Data input MSB, selects ROM, page 1

or 2

Cascading the PLCD558X Displays

WR

FL

RST

VCC

WR FL RST CLK I/O CLKSEL

Display

D0-D7 A0-A4

CE

Up to14 More Displays

in between

WR FL RST CLK I/O CLKSEL

Display

D0-D7 A0-A4

CE

Data I/O

Address

A6

0

A7

Address

A8

Decoder Address Decode Chip 1 to 14

A9

15

2–135

PLCD5580/1/2/3/4

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