PLCD5580 データシートの表示（PDF） - Infineon Technologies
部品番号
コンポーネント説明
メーカー
PLCD5580
Infineon Technologies
PLCD5580 Datasheet PDF : 12 Pages
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Data Input Commands
Signals
Operation
CE WR FL A3 A2 A1 A0
1
x
x
x
x
x
x
No operation
X
1
x
x
x
x
x
No operation
0 0 1 0 0 0 0 Write Control Register
0 0 1 1 0 0 0 Digit 0 (left)
0 0 1 1 0 0 1 Digit 1
0 0 1 1 0 1 0 Digit 2
0 0 1 1 0 1 1 Digit 3
0 0 1 1 1 0 0 Digit 4
0 0 1 1 1 0 1 Digit 5
0 0 1 1 1 1 0 Digit 6
0 0 1 1 1 1 1 Digit 7 (right)
Write display data to user RAM
and Page Select Register
D0–D6=ASCII Data
D7=0 Select ROM1
D7=1 Select ROM 2
0 0 0 X 0 0 0 Digit 0 (left)
0 0 0 X 0 0 1 Digit 1
0 0 0 X 0 1 0 Digit 2
0 0 0 X 1 1 1 Digit 3
0 0 0 X 1 0 0 Digit 4
0 0 0 X 1 0 1 Digit 5
0 0 0 X 1 1 0 Digit 6
0 0 0 X 1 1 1 Digit 7 (right)
X=don’t care
Write Flash RAM Register
D0=0 Flashing Character off
D0=1 Flashing Character on
D1–D7=X
Power up Sequence
Upon power up display will come on at random. Thus the
display should be reset on power-up. The reset will clear the
Flash RAM, Control Word Register and reset the internal
counter. All the digits will show blanks and display brightness
level will be 100%.
Microprocessor Interface
The interface to a microprocessor is through the 8-bit data
bus (D0-D7), the 4-bit address bus (A0–A3) and control lines
FL, CE and WR.
To write data (ASCII/ Control Word) into the display CE
should be held low, address and data signals stable and WR
should be brought low.
The Control Word is decoded by the Control Word Decode
Logic. Each code has a different function. The code for dis-
play brightness changes the duty cycle for the column driv-
ers. The peak LED current stays the same but the average
LED current diminishes depending on the intensity level.
The character Flash Enable causes 2 Hz coming out of the
counter to be ANDED with column drive signal and makes
the column driver to cycle at 2 Hz. Thus the character flashes
at 2 Hz.
The display Blink works the same way as the Flash Enable
but causes all twenty column drivers to cycle at 2 Hz thereby
making all eight digits to blink at 2 Hz.
The Lamp Test causes the column drivers to run at 1/2 duty
cycle thus all the LEDs in all eight digits turn on at 50% inten-
sity.
Clear bit clears the character RAM and writes a blank into
the display memory. It however does not clear the control
word.
ASCII Data or Control Word Data can be written into the dis-
play at this point. For multiple display operation, CLK I/O
must be properly selected. CLK I/O will output the internal
clock if CLKSEL=1, or will allow input from an external clock
if CLKSEL=0.
2–139
PLCD5580/1/2/3/4
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