QL8150-8PS484C(2002) データシートの表示（PDF） - QuickLogic Corporation

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QL8150-8PS484C
(Rev.:2002)

Low Power FPGA Combining Performance, Density, and Embeded RAM

QuickLogic Corporation 

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RESET

S1

S2

S3

CIN

SIGN1

SIGN2

A[7:0]

A[15:8]

A[0:15]

CLK

B[0:15]

D

C

3-4

decoder

B

A

8-bit

2-1

Multiplier

mux

2-1

mux

16-bit

Adder

DQ

17-bit

Register

00

01 3-1

mux

10

Q[16:0]

)LJXUH  (&8 %ORFN 'LDJUDP

The Eclipse-II ECU blocks ( 7DEOH ) are placed next to the SRAM circuitry for efficient

memory/instruction fetch and addressing for DSP algorithmic implementations.

7DEOH  (FOLSVH,, (&8 %ORFNV

'HYLFH

(&8V

QL8325

12

QL8250

10

QL8150

0

QL8050

0

QL8025

0

Up to twelve 8-bit MAC functions can be implemented per cycle for a total of 1 billion MACs/s

when clocked at 100 MHz. Additional multiply-accumulate functions can be implemented in the

programmable logic.



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