QL8150-8PS484C(2002) データシートの表示（PDF） - QuickLogic Corporation

部品番号

コンポーネント説明

メーカー

QL8150-8PS484C
(Rev.:2002)

Low Power FPGA Combining Performance, Density, and Embeded RAM

QuickLogic Corporation 

(FOLSVH,, )DPLO\ 'DWD 6KHHW 5HY %

The modes for the ECU block are dynamically re-programmable through the programmable logic.

,QVWUXFWLRQ

6 6 6

7DEOH  (&8 0RGH 6HOHFW &ULWHULD

2SHUDWLRQ

(&8 3HUIRUPDQFHD  :&&

W3'

W68

W&2

00 0

Multiply

6.6 ns max

00 1

01 0

Multiply-Add

Accumulateb

8.8 ns max

3.9 ns min

1.2 ns max

01 1

10 0

Add

Multiply (registered)c

3.1 ns max

9.6 ns min

1.2 ns max

1 0 1 Multiply- Add (registered)

9.6 ns min

1.2 ns max

1 1 0 Multiply - Accumulate

9.6 ns min

1.2 ns max

11 1

Add (registered)

3.9 ns min

1.2 ns max

a. tPD, tSU and tCO do not include routing paths in/out of the ECU block.

b. Internal feedback path in ECU restricts max clk frequency to 238 MHz.

c. B [15:0] set to zero.

NOTE: 7LPLQJ QXPEHUV LQ 7DEOH  UHSUHVHQW  :RUVW &DVH &RPPHUFLDO FRQGLWLRQV

3KDVH /RFNHG /RRS 3// ,QIRUPDWLRQ

Instead of requiring extra components, designers simply need to instantiate one of the pre-

configured models (described in this section). The QuickLogic built-in PLLs support a wider range

of frequencies than many other PLLs. These PLLs also have the ability to support different ranges

of frequency multiplications or divisions, driving the device at a faster or slower rate than the

incoming clock frequency. When PLLs are cascaded, the clock signal must be routed off-chip

through the PLLPAD_OUT pin prior to routing into another PLL; internal routing cannot be used

for cascading PLLs.

PLLs achieve a very short clock-to-out time—generally less than 3 ns. This low clock-to-out time

is achieved by the PLL subtracting the clock tree delay through the feedback path, effectively

making the clock tree delay zero.

Preliminary ‹  4XLFN/RJLF &RUSRUDWLRQ

ZZZTXLFNORJLFFRP ‡‡‡‡‡‡



Share Link: