LTC2655BCUF-H16-TRPBF データシートの表示（PDF） - Linear Technology
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LTC2655BCUF-H16-TRPBF
Linear Technology
LTC2655BCUF-H16-TRPBF Datasheet PDF : 28 Pages
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LTC2655
ELECTRICAL CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V (LTC2655B-L16/LTC2655-L12), VCC = 4.5V to 5.5V
(LTC2655B-H16, LTC2655-H12), VOUT unloaded unless otherwise specified.
LTC2655B-L16/LTC2655-L12/LTC2655B-H16/LTC2655-H12
SYMBOL PARAMETER
CONDITIONS
MIN TYP MAX UNITS
AC Performance
ts
Settling Time ( Note 10)
±0.024%(±1LSB at 12 Bits)
±0.0015%(±1LSB at 16 Bits)
3.9
μs
9.1
μs
Settling Time for 1LSB Step
±0.024%(±1LSB at 12 Bits)
±0.0015%(±1LSB at 16 Bits)
2.4
μs
4.5
μs
Voltage Output Slew Rate
1.8
V/μs
Capacitive Load Driving
1000
pF
Glitch Impulse (Note 11)
At Mid-Scale Transition, -L Option
4
nV•s
At Mid-Scale Transition, -H Option
7
nV•s
DAC to DAC Crosstalk (Note 12)
CREFCOMP = CREFIN/OUT = 0.22μF
0.5
nV•s
Multiplying Bandwidth
en
Output Voltage Noise Density
At f = 1kHz
At f = 10kHz
150
kHz
85
nV/√Hz
80
nV/√Hz
Output Voltage Noise
0.1Hz to 10Hz, Internal Reference (-L Options)
0.1Hz to 10Hz, Internal Reference (-H Options)
0.1Hz to 200KHz, Internal Reference (-L Options)
0.1Hz to 200KHz, Internal Reference (-H Options)
8
μVP-P
12
μVP-P
400
μVP-P
450
μVP-P
TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. VCC = 2.7V to 5.5V (LTC2655B-L16/LTC2655-L12), VCC = 4.5V to 5.5V (LTC2655B-H16,
LTC2655-H12), VOUT unloaded unless otherwise specified.
LTC2655B-L16/LTC2655-L12/LTC2655B-H16/LTC2655-H12 (see Figure 1)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP MAX
UNITS
fSCL
tHD(STA)
tLOW
tHIGH
tSU(STA)
tHD(DAT)
tSU(DAT)
tr
tf
tSU(STO)
tBUF
t1
t2
SCL Clock Frequency
Hold Time (Repeated) Start Condition
Low Period of the SCL Clock Pin
High Period of the SCL Clock Pin
Set-Up Time for a Repeated Start Program
Data Hold Time
Data Set-Up Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-Up Time for Stop Condition
Bus Free Time Between a Stop and Start Condition
Falling edge of the 9th Clock of the 3rd Input Byte
to LDAC High or Low Transition
LDAC Low Pulse Width
(Note 13)
(Note 13)
l
0
l
0.6
l
1.3
l
0.6
l
0.6
l
0
l
100
l 20+0.1CB
l 20+0.1CB
l
0.6
l
1.3
l
400
l
20
400
kHz
μs
μs
μs
μs
0.9
μs
ns
300
ns
300
ns
μs
μs
ns
ns
2655f
9
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