73K324L-28IFR データシートの表示（PDF） - Teridian Semiconductor Corporation
部品番号
コンポーネント説明
メーカー
73K324L-28IFR
Teridian Semiconductor Corporation
73K324L-28IFR Datasheet PDF : 30 Pages
| |||
REGISTER DESCRIPTIONS
Eight 8-bit internal registers are accessible for
control and status monitoring. The registers are
accessed in read or write operations by addressing
the A0, A1 and A2 address lines in Serial mode, or
the AD0, AD1 and AD2 lines in Parallel mode. The
address lines are latched by ALE. Register CR0
controls the method by which data is transferred
over the phone line. CR1 controls the interface
between the microprocessor and the 73K324L
73K324L
CCITT V.22bis,V.23,V.22,V.21, Bell 212A
Single-Chip Modem
DATA SHEET
internal state. DR is a detect register which provides
an indication of monitored modem status conditions.
TR, the tone control register, controls the DTMF
generator, answer, guard tones, SCT, calling tone,
and RXD output gate used in the modem initial
connect sequence. CR2 is the primary DSP control
interface and CR3 controls transmit attenuation and
receive gain adjustments. All registers are read/write
except for DR and ID, which are read only. Register
control and status bits are identified below:
REGISTER BIT SUMMARY
ADDRESS
DATA BIT NUMBER
REGISTER
AD - A0
D7
D6
D5
D4
D3
CONTROL
REGISTER CR0
000
0
CONTROL
REGISTER CR1
001
1
DETECT
REGISTER
DR
010
TONE
CONTROL
TR
011
REGISTER
CONTROL
REGISTER CR2
100
2
CONTROL
REGISTER CR3
101
3
MODULATION
OPTION
TRANSMIT
PATTERN
1
MODULATION
TYPE
1
TRANSMIT
PATTERN
0
MODULATION
TYPE
0
ENABLE
DETECT
INTERRUPT
TRANSMIT
MODE
2
BYPASS
SCRAMBLER/
ADD PH. EQ.
(V.23)
RECEIVE
LEVEL
RXD
OUTPUT
CONTROL
PATTERN
S1 DET
RECEIVE
DATA
TRANSMIT
GUARD TONE/
SCT/CALLING
TONE
TRANSMIT
ANSWER
TONE
UNSCR.
MARK
DETECT
TRANSMIT
DTMF
0
SPECIAL
REGISTER
CALL
INITIALIZE
TRANSMIT
S1
ACCESS
TXDALT
TRISTATE
TX/RXCLK
0
RECEIVE
GAIN
BOOST
TRANSMIT
MODE
1
CLK
CONTROL
CARRIER
DETECT
DTMF3
16 WAY
TRANSMIT
ATTEN.
3
SPECIAL
REGISTER SR
101
0
TX BAUD
RX UNSCR.
0
CLOCK
DATA
TXD
SOURCE
ID
REGISTER
ID
110
1
1
1
0
X
D2
TRANSMIT
MODE
0
RESET
SPECIAL
TONE
DETECT
DTMF2/
4 WIRE FDX
RESET
DSP
TRANSMIT
ATTEN.
2
SQ
SELECT 1
X
D1
TRANSMIT
ENABLE
D0
ANSWER/
ORIGINATE
TEST
MODE
1
TEST
MODE
0
CALL
PROGRESS
DETECT
SIGNAL
QUALITY
DTMF1/
OVERSPEED
DTMF0/GUARD/
ANSWER/
CALLING/SCT
TRAIN
INHIBIT
TRANSMIT
ATTEN.
1
SQ
SELECT 0
EQUALIZER
ENABLE
TRANSMIT
ATTEN.
0
0
X
X
NOTE: When a register containing reserved control bits is written into, the reserved bits must be programmed as
0's.
X = Undefined, mask in software.
Page: 6 of 30
© 2005, 2008 TERIDIAN Semiconductor Corporation
Rev 7.1
Share Link: