IDT72420L12TP データシートの表示（PDF） - Integrated Device Technology
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IDT72420L12TP
Integrated Device Technology
IDT72420L12TP Datasheet PDF : 16 Pages
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO™
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
PIN CONFIGURATION
D4 1
D3 2
D2 3
D1 4
D0 5
AF 6
AE 7
GND 8
RCLK 9
REN 10
OE 11
EF 12
FF 13
Q0 14
MILITARY AND COMMERCIAL TEMPERATURE RANGES
P28-2
C28-1
DIP TOP
VIEW
28 D5
27 D6
26 D7
25 RS
24 WEN
23 WCLK
22 VCC
21 Q7
20 Q6
19 Q5
18 Q4
17 Q3
16 Q2
15 Q1
2680 drw 02
PIN DESCRIPTIONS
Symbol
Name
I/O
D0 - D7 Data Inputs
I
RS
Reset
I
WCLK Write Clock
I
WEN
Write Enable
I
Q0 - Q7 Data Outputs O
RCLK
Read Clock
I
REN
Read Enable
I
OE
Output Enable I
EF
Empty Flag
O
AE
Almost-Empty O
Flag
AF
Almost-Full Flag O
FF
Full Flag
O
VCC
GND
Power
Ground
Description
Data inputs for a 8-bit bus.
When RS is set LOW, internal read and write pointers are set to the first location of the RAM
array, FF and AF go HIGH, and AE and EF go LOW. A reset is required before an initial WRITE
after power-up.
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when WEN is asserted.
When WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK.
Data will not be written into the FIFO if the FF is LOW.
Data outputs for a 8-bit bus.
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when REN is asserted.
When REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the EF is LOW.
When OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a
high-impedance state.
When EF is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF is HIGH, the FIFO is not empty. EF is synchronized to RCLK.
When AE is LOW, the FIFO is almost empty based on the offset Empty+7. AE is synchronized
to RCLK.
When AF is LOW, the FIFO is almost full based on the offset Full-7. AF is synchronized to
WCLK.
When FF is LOW, the FIFO is full and further data writes into the input are inhibited. When FF is
HIGH, the FIFO is not full. FF is synchronized to WCLK.
One +5 volt power supply pin.
One 0 volt ground pin.
2680 tbl 01
5.12
2
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