IDT72420L12TP データシートの表示（PDF） - Integrated Device Technology
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IDT72420L12TP
Integrated Device Technology
IDT72420L12TP Datasheet PDF : 16 Pages
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IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO™
64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8
MILITARY AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to + 70°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
Symbol Parameter
Commercial
72220L12 72220L15
72230L12 72230L15
72240L12 72240L15
Min. Max. Min. Max.
Commercial & Military
72220L20 72220L25
72230L20 72230L25
72240L20 72240L25
Min. Max. Min. Max.
Comm.
72220L35
72230L35
72240L35
Min. Max.
Comm./Mil.
72220L50
72230L50
72240L50
Min. Max.
fS
Clock Cycle Frequency
— 83.3 — 66.7 — 50 — 40 — 28.6 — 20
tA
Data Access Time
2
8
2
10
2
12
3
15
3
20
3
25
tCLK Clock Cycle Time
12 — 15 — 20 — 25 — 35 — 50 —
tCLKH Clock High Time
5
—
6
—
8
— 10 — 14 — 20 —
tCLKL Clock Low Time
5
—
6
—
8
— 10 — 14 — 20 —
tDS
Data Set-up Time
3
—
4
—
5
—
6
—
8
— 10 —
tDH
Data Hold Time
.5
—
1
—
1
—
1
—
2
—
2
—
tENS Enable Set-up Time
3
—
4
—
5
—
6
—
8
— 10 —
tENH Enable Hold Time
.5
—
1
—
1
—
1
—
2
—
2
—
tRS
Reset Pulse Width(1)
12 — 15 — 20 — 25 — 35 — 50 —
tRSS Reset Set-up Time
12 — 15 — 20 — 25 — 35 — 50 —
tRSR Reset Recovery Time
12 — 15 — 20 — 25 — 35 — 50 —
tRSF Reset to Flag and Output Time
— 12 — 15 — 20 — 25 — 35 — 50
tOLZ Output Enable to Output in Low-Z(2)
0
—
0
—
0
—
0
—
0
—
0
—
tOE
Output Enable to Output Valid
3
7
3
8
3 10 3 13 3 15 3 23
tOHZ Output Enable to Output in High-Z(2) 3
7
3
8
3 10 3 13 3 15 3 23
tWFF Write Clock to Full Flag
—
8
— 10 — 12 — 15 — 20 — 30
tREF Read Clock to Empty Flag
—
8
— 10 — 12 — 15 — 20 — 30
tAF
Write Clock to Almost-Full Flag
—
8
— 10 — 12 — 15 — 20 — 30
tAE
Read Clock to Almost-Empty Flag
—
8
— 10 — 12 — 15 — 20 — 30
tSKEW1 Skew time between Read Clock
& Write Clock for Empty Flag &
Full Flag
tSKEW2 Skew time between Read Clock &
Write Clock for Almost-Empty Flag
& Almost-Full Flag
5
—
6
—
8
— 10 — 12 — 15 —
22 — 28 — 35 — 40 — 42 — 45 —
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
5V
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2680 tbl 08
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1
2680 tbl 09
D.U.T.
680Ω
1.1KΩ
30pF*
2680 drw 03
or equivalent circuit
Figure 1. Output Load
*Includes jig and scope capacitances.
5.12
5
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