IDT72420L12TP データシートの表示（PDF） - Integrated Device Technology

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IDT72420L12TP

CMOS SyncFIFO™ 64 x 8, 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8

Integrated Device Technology 

IDT72420/72200/72210/72220/72230/72240 CMOS SyncFIFO™

64 X 8, 256 X 8, 512 X 8, 1024 X 8, 2048 X 8 and 4096 X 8

WCLK

tCLKH

tCLK

tCLKL

tDS

D0 - D7

WEN

FF

DATAIN VALID

tENS

tWFF

tSKEW1 (1)

RCLK

MILITARY AND COMMERCIAL TEMPERATURE RANGES

tDH

tENH

tWFF

NO OPERATION

REN

2680 drw 05

NOTE:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge for FF to change during the curent clock cycle. If the time between

the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then FF may not change state until the next WCLK edge.

Figure 3. Write Cycle Timing

5.12

8

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