AMS2263 データシートの表示（PDF） - Advanced Monolithic Systems Inc

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AMS2263

highly integrated current mode PWM control IC

Advanced Monolithic Systems Inc 

AMS 2263

sense input is no longer required. The current

limit comparator is disabled and thus cannot turn

off the external MOSFET during the blanking

period. PWM duty cycle is determined by the

current sense input voltage and the FB input

voltage.

•Internal Synchronized Slope Compensation

Built-in slope compensation circuit adds voltage

ramp onto the current sense input voltage for

PWM generation. This greatly improves the close

loop stability at CCM and prevents the

sub-harmonic oscillation and thus reduces the

output ripple voltage.

• Gate Drive

AMS2263 Gate is connected to an external

MOSFET gate for power switch control. Too weak

the gate drive strength results in higher

conduction and switch loss of MOSFET while too

strong gate drive output compromises the EMI.

A good tradeoff is achieved through the built-in

totem pole gate design with right output strength

and dead time control. The low idle loss and good

EMI system design is easier to achieve with this

dedicated control scheme. An internal 18V clamp

is added for MOSFET gate protection at higher

than expected VDD input.

• Protection Controls

Good power supply system reliability is achieved

with its rich protection features including

Cycle-by-Cycle current limiting (OCP), Over Load

Protection (OLP) and over voltage clamp, Under

Voltage Lockout on VDD (UVLO).

The OCP threshold tracks PWM Duty cycles and

is line voltage compensated to achieve constant

output power limit over the universal input voltage

range with recommended reference design.

At overload condition when FB input voltage

exceeds power limit threshold value for more than

TD_PL, control circuit reacts to shut down the

output power MOSFET. Device restarts when

VDD voltage drops below UVLO limit.

VDD is supplied by transformer auxiliary winding

output. It is clamped when VDD is higher than

threshold value. The power MOSFET is shut

down when VDD drops below UVLO limit and

device enters power on start-up sequence

thereafter.

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Advanced Monolithic Systems http://www.ams-semitech.com

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