1N4148W データシートの表示（PDF） - Silicon Laboratories

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1N4148W

ISOLATED EVALUATION BOARD FOR THE Si3402B

Silicon Laboratories 

Si3402BISO-EVB

APPENDIX—Si3402BISO DESIGN AND LAYOUT

CHECKLIST

Introduction

Although all four EVB designs are preconfigured as Class 3 PDs with 5 V outputs, the schematics and layouts can

easily be adapted to meet a wide variety of common output voltages and power levels.

The complete EVB design databases for the standard 5 V/Class 3 configuration are included in the EVB kit and

can also be requested through Silicon Labs customer support at www.silabs.com/PoE under the “Documentation”

link. Silicon Labs strongly recommends using these EVB schematics and layout files as a starting point to ensure

robust performance and to help avoid common mistakes in the schematic capture and PCB layout processes.

Following are recommended design checklists that can assist in trouble-free development of robust PD designs:

Refer also to the Si3402B data sheet and AN956 when using the checklists below.

1. Design Planning Checklist:

a. Silicon Labs strongly recommends using the EVB schematics and layout files as a starting point as you

begin integrating the Si3402B into your system design process.

b. Determine your load’s power requirements (i.e., VOUT and IOUT consumed by the PD, including the

typical expected transient surge conditions). In general, to achieve the highest overall efficiency

performance of the Si3402, choose the highest voltage used in your PD and then post regulate to the

lower supply rails, if necessary.

c. If your PD design consumes >7 W, make sure you bypass the Si3402’s on-chip diode bridges with

external Schottky diode bridges or discrete Schottky diodes. Bypassing the Si3402’s on-chip diode

bridges with external bridges or discrete diodes is required to help spread the heat generated in designs

dissipating >7 W.

d. Based on your required PD power level, select the appropriate class resistor value by referring to Table 3

of AN956. This sets the Rclass resistor (R3 in Figure 1 on page 2).

e. The feedback loop stability has been checked over the entire load range for the specific component

choices in Table 1. Low ESR filter capacitors will give better load transient response and lower output

ripple so they are generally preferred. For the standard ESR capacitor, the ESR increase at very low

temperatures may cause a loop stability issue. A typical evaluation board has been shown to exhibit

instability under very heavy loads at –20 °C. Due to self-heating, this condition is not a great concern.

However, using a low ESR filter capacitor solves this problem (but requires some recompensation of the

feedback loop). Silicon Laboratories recommends against component substitution in the filtering and

feedback path as this may result in unstable operation. Also, use care in situations that have additional

capacitive loading as this will also affect loop stability.

2. General Design Checklist Items:

a. ESD caps (C10–C17 in Figure 1) are strongly recommended for designs where system-level ESD

(IEC6100-4-2) must provide >15 kV tolerance.

b. If your design uses an AUX supply, make sure to include a 3  surge limiting resistor in series with the

AUX supply for hot insertion. Refer to AN956 when AUX supply is 48 V.

c. Silicon Labs strongly recommends the inclusion of a minimum load (250 mW) to avoid switcher pulsing

when no load is present, and to avoid false disconnection when less than 10 mA is drawn from the PSE.

If your load is not at least 250 mW, add a resistor load to dissipate at least 250 mW.

d. If using PLOSS function, make sure it’s properly terminated for connection in your PD subsystem. If

PLOSS is not needed, leave this pin floating.

Rev. 1.2

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