C8051F231 データシートの表示（PDF） - Unspecified

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C8051F231

8K Flash, 256 RAM, 32-Pin MCU

Unspecified 

C8051F231

ANALOG PERIPHERALS

Two Comparators

- Programmable Hysteresis

- Configurable to Generate Interrupts or Reset

VDD Monitor and Brown-out Detector

ON-CHIP JTAG DEBUG

- On-Chip Debug Circuitry Facilitates Full Speed,

Non-Intrusive In-System Debug (No Emulator

Required!)

- Provides Breakpoints, Single Stepping,

Watchpoints, Stack Monitor

- Inspect/Modify Memory and Registers

- Superior Performance to Emulation Systems Using

ICE-Chips, Target Pods, and Sockets

- Low Cost, Complete Development Kit

SUPPLY VOLTAGE ......................2.7V to 3.6V

- Typical Operating Current: 9mA @ 25MHz

- Typical Stop Mode Current: <0.1uA

Temperature Range: –40°C to +85°C

32-Pin LQFP Package

8K Flash, 256 RAM, 32-Pin MCU

PRELIMINARY

8051-COMPATIBLE µC Core

- Pipelined Instruction Architecture; Executes 70%

of Instructions in 1 or 2 System Clocks

- Up to 25MIPS Throughput with 25MHz Clock

- Expanded Interrupt Handler

MEMORY

- 256 Bytes Data RAM

- 8k Bytes FLASH; In-System Programmable in 512

byte Sectors

DIGITAL PERIPHERALS

- 22 Port I/O; All are 5V tolerant

- Hardware SPITM and UART Serial Ports Available

Concurrently

- Three 16-bit Counter/Timers

- Dedicated Watch-Dog Timer

- Bi-directional Reset

CLOCK SOURCES

- Internal Programmable Oscillator: 2-to-16MHz

- External Oscillator: Crystal, RC, C, or Clock

- Can Switch Between Clock Sources on-the-fly;

Useful in Power Saving Modes

SPI is a trademark of Motorola, Inc.

Analog/Digital

VDD

Power

GND

TCK

TMS

TDI

TDO

/RST

XTAL1

XTAL2

JTAG

Logic

VDD

Monitor

External

Oscillator

Circuit

Internal

Oscillator

Debug HW

8

0

5 Reset

1

WDT

C

o

r System Clock

e

8kbyte

FLASH

256 byte

RAM

SFR Bus

Port 0

Latch

P

UART

0

Timer 0

M

Timer 1

U

X

Timer 2

Port 1

Latch

CP0

CP0

CP1

CP1

P

CP0+

1

CP0-

M

U

CP1+

X

CP1-

SYSCLK

Port 2

P

2

Latch

SPI

M

U

X

Port 3

Latch

P

P0.0/TX

0

P0.1/RX

P0.2//INT0

P0.3//INT1

D

P0.4/T0

r

P0.5/T1

v

P0.6/T2

P0.7/T2EX

P

P1.0/CP0+

1

P1.1/CP0-

P1.2/CP0

P1.3/CP1+

D

P1.4/CP1-

r

P1.5/CP1

v

P1.6/SYSCLK

P1.7

P

P2.0/SCK

2

P2.1/MISO

P2.2/MOSI

P2.3/NSS

D

P2.4

r

P2.5

v

P

3

D

r

v

NC

7.15.2002

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