FH8065501516753SR1UM データシートの表示（PDF） - Intel
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FH8065501516753SR1UM Datasheet PDF : 745 Pages
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Contents—C2000 Product Family
15.8.2 Registers in Memory Space .................................................................. 353
16 Platform Controller Unit (PCU)............................................................................... 355
16.1 Features ........................................................................................................ 356
16.2 Pin-Based (Hard) Straps................................................................................... 357
16.3 Multi-Functional Signal Pins .............................................................................. 360
16.3.1 Pins with More Than One Native Function ............................................... 360
16.3.2 Pins of the Ethernet NC-SI Interface ...................................................... 361
16.4 Soft Straps ..................................................................................................... 362
16.4.1 Flash Descriptor Soft Strap Definition .................................................... 362
16.5 Root Complex Register Block (RCRB) ................................................................. 372
16.5.1 Boot BIOS Straps (BBS)....................................................................... 372
16.6 BIOS Ranges on Flash Memory Devices .............................................................. 373
16.6.1 BIOS Decode Enable for LPC and SPI ..................................................... 373
16.7 Register Map .................................................................................................. 374
16.7.1 PCI Configuration and Capabilities ......................................................... 375
16.7.2 MMIO Registers .................................................................................. 375
16.7.3 Alternate Register Access Map .............................................................. 375
17 SMBus 2.0 Unit 2 - PECI ......................................................................................... 377
17.1 Signal Descriptions .......................................................................................... 378
17.2 PECI over SMBus Features................................................................................ 378
17.3 SMBus Supported Transactions ......................................................................... 379
17.4 SMBus Block Read/Write Transaction Formats ..................................................... 380
17.5 SMBus Commands........................................................................................... 381
17.6 PECI Over SMBus ............................................................................................ 382
17.6.1 PECI Message Header in SMBus ............................................................ 382
17.6.1.1
17.6.1.2
17.6.1.3
Target Address Field ........................................................... 383
Write Length Field .............................................................. 383
Read Length Field............................................................... 383
17.6.1.4 Command Byte .................................................................. 383
17.6.2 PECI Write-Read Protocol ..................................................................... 384
17.6.2.1 PECI Proxy Command Format .............................................. 385
17.6.2.2 PECI Proxy Read Command ................................................. 386
17.6.3 PECI Proxy Command Handling Procedure .............................................. 388
17.6.4 PECI Proxy Command Trigger ............................................................... 389
17.6.4.1 Unsupported PECI Command ............................................... 389
17.6.4.2 Illegally Formatted Command .............................................. 389
17.7 PECI Proxy Commands..................................................................................... 390
17.7.1 Ping()................................................................................................ 391
17.7.2 GetDIB() ........................................................................................... 393
17.7.2.1 PECI Device Info Field ......................................................... 395
17.7.2.2 PECI Revision Number ........................................................ 395
17.7.3 GetTemp() ......................................................................................... 396
17.7.4 RdPkgConfig() .................................................................................... 398
17.7.5 WrPkgConfig() .................................................................................... 400
17.7.6 RdPCIConfigLocal() ............................................................................. 403
17.7.7 RdEndPointConfig() ............................................................................. 405
17.7.8 WrEndPointConfig()............................................................................. 407
17.8 DRAM Thermal Capabilities ............................................................................... 410
17.8.1 DRAM Rank Temperature Write (Index = 18).......................................... 411
17.8.2 DRAM Channel Temperature Read (Index = 22) ...................................... 411
17.9 CPU Thermal and Power Optimization Capabilities ................................................ 412
17.9.1 Package Identifier Read (Index = 0) ...................................................... 416
17.9.1.1 CPU ID Information ............................................................ 416
17.9.1.2 Platform ID........................................................................ 416
January 2016
Order Number: 330061-003US
Intel® Atom™ Processor C2000 Product Family for Microserver
Datasheet
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