FH8065501516754SR1UN データシートの表示（PDF） - Intel
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FH8065501516754SR1UN Datasheet PDF : 745 Pages
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Contents—C2000 Product Family
13 SATA Controllers (SATA2, SATA3) ..........................................................................246
13.1 Signal Descriptions .......................................................................................... 247
13.2 Features ........................................................................................................ 248
13.2.1 Supported Features............................................................................. 248
13.2.2 Theory of Operation ............................................................................ 249
13.2.2.1 Standard ATA Emulation...................................................... 249
13.2.2.2 48-Bit LBA Operation .......................................................... 249
13.2.3 SATA Swap Bay Support ...................................................................... 249
13.2.4 Function Level Reset Support (FLR) ....................................................... 250
13.2.4.1 FLR Steps.......................................................................... 250
13.2.5 Power Management Operation .............................................................. 251
13.2.5.1
13.2.5.2
13.2.5.3
Power State Mappings......................................................... 251
Power State Transitions....................................................... 251
SMI Trapping (APM)............................................................ 252
13.2.6 SATA Device Presence ......................................................................... 253
13.2.7 SATA LED .......................................................................................... 253
13.2.8 AHCI Operation .................................................................................. 254
13.2.9 External SATA .................................................................................... 254
13.3 Staggered Spin-Up Support .............................................................................. 255
13.3.1 Staggered Spin-Up Operations in IDE Mode ............................................ 255
13.3.2 Staggered Spin-Up Operation in AHCI Mode ........................................... 255
13.4 Register Map .................................................................................................. 256
13.5 PCI Configuration Registers .............................................................................. 257
13.6 Bus Master IDE I/O Registers ............................................................................ 259
13.7 Serial ATA Index/Data Pair Superset Registers .................................................... 259
13.8 Memory-Mapped Registers................................................................................ 260
14 Universal Serial Bus (USB) 2.0 ............................................................................... 262
14.1 Signal Descriptions .......................................................................................... 263
14.2 Feature List .................................................................................................... 263
14.3 Architectural Overview ..................................................................................... 264
14.3.1 PCI Configuration Registers .................................................................. 266
14.3.2 Memory-Mapped I/O Registers.............................................................. 267
14.3.2.1 Host Controller Capability Registers ...................................... 267
14.3.2.2 Host Controller Operational Registers .................................... 268
14.4 Enhanced Host Controller DMA .......................................................................... 269
14.5 Data Encoding and Bit Stuffing .......................................................................... 270
14.6 Packet Formats ............................................................................................... 270
14.7 EHC Initialization............................................................................................. 270
14.7.1 Power-On .......................................................................................... 270
14.7.2 BIOS Initialization ............................................................................... 270
14.7.3 Port Disable Override .......................................................................... 271
14.7.4 Driver Initialization ............................................................................. 271
14.7.5 EHC Resets ........................................................................................ 271
14.8 Sequence and Operating Modes......................................................................... 272
14.9 Interrupts and Error Conditions ......................................................................... 273
14.9.1 Aborts on USB 2.0-Initiated Memory Reads ............................................ 273
14.10 Power Management ......................................................................................... 274
14.10.1 Advanced Configuration and Power Interface (ACPI) ................................ 274
14.10.1.1 ACPI System States............................................................ 275
14.10.2 Wake from System Suspend................................................................. 275
14.10.3 Asynchronous Extended Sleep .............................................................. 275
14.10.4 EHCI Prefetch-Based Pause .................................................................. 275
14.10.5 EHCI Descriptor Cache......................................................................... 276
14.10.6 USB Internal Clock Shut Down.............................................................. 276
January 2016
Order Number: 330061-003US
Intel® Atom™ Processor C2000 Product Family for Microserver
Datasheet
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