ADT7467ARQ-REEL データシートの表示（PDF） - ON Semiconductor
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ADT7467ARQ-REEL Datasheet PDF : 72 Pages
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ADT7467
Table 3. ELECTRICAL SPECIFICATIONS (TA = TMIN to TMAX, VCC = VMIN to VMAX, unless otherwise noted.) (Note 1)
Parameter
Test Conditions/Comments
Min
Typ
Max Unit
SMBus DIGITAL INPUTS (SCL, SDA)
Input High Voltage, VIH
Input Low Voltage, VIL
Hysteresis
2.0
−
−
−
−
500
−
V
0.4
V
−
mV
DIGITAL INPUT LOGIC LEVELS (TACH INPUTS)
Input High Voltage, VIH
Maximum Input Voltage
2.0
−
−
V
−
−
5.5
Input Low Voltage, VIL
Minimum Input Voltage
−
−
−0.3
−
0.8
V
−
Hysteresis
−
0.5
−
V p−p
DIGITAL INPUT LOGIC LEVELS (THERM) ADTL+
Input High Voltage, VIH
Input Low Voltage, VIL
DIGITAL INPUT CURRENT
−
0.75 VCCP
−
V
−
−
0.4
V
Input High Current, IIH
Input Low Current, IIL
Input Capacitance, CIN
SERIAL BUS TIMING
VIN = VCC
VIN = 0
−1
−
−
−
−
5
−
mA
1
mA
−
pF
Clock Frequency, fSCLK
10
−
400
kHz
Glitch Immunity, tSW
−
−
50
ns
Bus Free Time, tBUF
4.7
−
−
ms
Start Setup Time, tSU; STA
4.7
−
−
ms
Start Hold Time, tHD; STA
4.0
−
−
ms
SCL Low Time, tLOW
4.7
−
−
ms
SCL High Time, tHIGH
4.0
−
50
ms
SCL, SDA Rise Time, tr
−
−
1000
ns
SCL, SDA Fall Time, tf
−
−
300
ms
Data Setup Time, tSU; DAT
250
−
−
ns
Data Hold Time, tHD; DAT
300
−
−
ns
Detect Clock Low Timeout, tTIMEOUT
Can be Optionally Disabled
15
−
35
ms
1. All voltages are measured with respect to GND, unless otherwise specified. Typicals are at TA = 25C and represent the most likely
parametric norm. Logic inputs accept input high voltages up to VMAX even when the device is operating down to VMIN. Timing specifications
are tested at logic levels of VIL = 0.8 V for a falling edge and VIH = 2.0 V for a rising edge. SMBus timing specifications are guaranteed by
design and are not production tested.
SCL
SDA
tBUF
P
S
t LOW
tR
tHD; STA
tHD; DAT
tF
tHIGH
tSU; DAT
t HD; STA
tSU; STA
S
Figure 2. Serial Bus Timing Diagram
tSU; STO
P
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