Test Diagrams (Continued)
nB n
V IN
GND
V IN
GND
RS
nA
CL
GND
VOUT
RL
tRISE= 2.5ns
Vcc
Input - VSel
10%
0V
V OUT
90%
Vcc/2
0.9*Vout
VSel RL and CL are functions of the application
tD
GND environment (see AC/DC tables).
CL includes test fixture and stray capacitance.
Figure 12. Break-Before-Make Interval Timing
0.9*Vout
Network Analyzer
RS
V IN
GND
VS
VS e l
GND
GND
GND
VOU T
RT
RL and CL are functions of the application
GND
environment (see AC/DC tables).
CL includLes test fixture and stray capacitance.
Figure 13. Bandwidth
Network Analyzer
RS
RT
GND
VS
VSel
GND
GND
GND
RS and RT are functions of the application
environment (see AC/DC tables).
GND
VOU T
RT
GND
Off-Isolation = 20 Log (VOUT / VIN )
Figure 14. Channel Off Isolation
© 2007 Fairchild Semiconductor Corporation
FSA2269 / FSA2269TS • Rev. 1.1.5
9
www.f airchildsemi.com