FT24C02A データシートの表示（PDF） - Unspecified

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FT24C02A

Two-Wire Serial EEPROM 2K (8-bit wide)

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FT24C02A

words are loaded, the 17th data word will be loaded to the 1st data word column address. The 18th

data word will be loaded to the 2nd data word column address and so on. In other word, data word

address (column address) will “roll” over the previously loaded data.

(C) ACKNOWLEDGE POLLING

ACKNOWLEDGE polling may be used to poll the programming status during a self-timed internal

programming. By issuing a valid read or write address command, the EEPROM will not acknowledge

at the 9th clock cycle if the device is still in the self-timed programming mode. However, if the

programming completes and the chip has returned to the STANDBY mode, the device will return a

valid ACKNOWLEDGE signal at the 9th clock cycle.

READ OPERATIONS

The read command is similar to the write command except the 8th read/write bit in address word is set to “1”.

The three read operation modes are described as follows:

(A) CURRENT ADDRESS READ

The EEPROM internal address word counter maintains the last read or write address plus one if the

power supply to the device has not been cut off. To initiate a current address read operation, the

micro-controller issues a START bit and a valid device address word with the read/write bit (8th) set to

“1”. The EEPROM will response with an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-

bit data word will then be serially clocked out. The internal address word counter will then

automatically increase by one. For current address read the micro-controller will not issue an

ACKNOWLEDGE signal on the 18th clock cycle. The micro-controller issues a valid STOP bit after

the 18th clock cycle to terminate the read operation. The device then returns to STANDBY mode.

(B) SEQUENTIAL READ

The sequential read is very similar to current address read. The micro-controller issues a START bit

and a valid device address word with read/write bit (8th) set to “1”. The EEPROM will response with

an ACKNOWLEDGE signal on the 9th serial clock cycle. An 8-bit data word will then be serially

clocked out. Meanwhile the internally address word counter will then automatically increase by one.

Unlike current address read, the micro-controller sends an ACKNOWLEDGE signal on the 18th clock

cycle signaling the EEPROM device that it wants another byte of data. Upon receiving the

ACKNOWLEDGE signal, the EEPROM will serially clocked out an 8-bit data word based on the

incremented internal address counter. If the micro-controller needs another data, it sends out an

ACKNOWLEDGE signal on the 27th clock cycle. Another 8-bit data word will then be serially clocked

out. This sequential read continues as long as the micro-controller sends an ACKNOWLEDGE signal

after receiving a new data word. When the internal address counter reaches its maximum valid

address, it rolls over to the beginning of the memory array address. Similar to current address read,

the micro-controller can terminate the sequential read by not acknowledging the last data word

received, but sending a STOP bit afterwards instead.

© 2009 Fremont Micro Devices Inc.

DS3011B-page7

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