SN74LS164D データシートの表示（PDF） - ON Semiconductor

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SN74LS164D

Serial-In Parallel-Out Shift Register

ON Semiconductor 

SN74LS164

CONNECTION DIAGRAM DIP (TOP VIEW)

VCC Q7 Q6 Q5 Q4 MR CP

14 13 12 11 10 9 8

NOTE:

The Flatpak version has the same

pinouts (Connection Diagram) as

the Dual In-Line Package.

1234567

A B Q0 Q1 Q2 Q3 GND

PIN NAMES

A, B

CP

MR

Q0 – Q7

Data Inputs

Clock (Active HIGH Going Edge) Input

Master Reset (Active LOW) Input

Outputs

NOTES:

a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.

LOADING (Note a)

HIGH

LOW

0.5 U.L.

0.5 U.L.

0.5 U.L.

10 U.L.

0.25 U.L.

0.25 U.L.

0.25 U.L.

5 U.L.

LOGIC SYMBOL

1A

LS164

2 B 8-BIT SHIFT REGISTER

8 CP

MR Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7

9 3 4 5 6 10 11 12 13

VCC = PIN 14

GND = PIN 7

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