MC74AC112D データシートの表示（PDF） - Motorola => Freescale
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MC74AC112D Datasheet PDF : 6 Pages
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MC74AC112
MC74ACT112
Dual JK Negative
EdgeĆTriggered FlipĆFlop
The MC74AC112/74ACT112 consists of two high-speed completely independent
transition clocked JK flip-flops. The clocking operation is independent of rise and fall
times of the clock waveform. The JK design allows operation as a D flip-flop (refer to
MC74AC74/74ACT74 data sheet) by connecting the J and K inputs together.
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q HIGH
• Outputs Source/Sink 24 mA
• ′ACT112 Has TTL Compatible Inputs
CONNECTION DIAGRAM
VCC CD1 CD2 CP2 K2
16 15 14 13 12
J2 SD2 Q2
11 10 9
K CD Q
CP
J
Q
SD
J SD Q
CP
K CD Q
DUAL JK NEGATIVE
EDGE-TRIGGERED
FLIP-FLOP
N SUFFIX
CASE 648-08
PLASTIC
D SUFFIX
CASE 751B-05
PLASTIC
1 2 3 4 5 6 78
CP1 K1 J1 SD1 Q1 Q1 Q2 GND
MODE SELECT — TRUTH TABLE
Operating Mode
Inputs
SD CD J K
Set
Reset (Clear)
*Undetermined
Toggle
Load “0” (Reset)
Load “1” (Set)
Hold
L
HXX
H
LXX
L
LXX
H
Hhh
H
Hl h
H
Hh
l
H
Hl
l
Outputs
Q
Q
H
L
L
H
H
H
q
q
L
H
H
L
q
q
*Both outputs will be HIGH while both SD and CD are LOW, but the output states
are unpredictable if SD and CD go HIGH simultaneously.
H, h = HIGH Voltage Level
L, l = LOW Voltage Level
X = Don’t Care
l, h (q) = Lower case letters indicate the state of the referenced input
(or output) one set-up time prior to the HIGH to LOW clock transition.
LOGIC SYMBOL
4
10
SD
SD
3
J
Q
5 11
J
Q
9
1 CP
13 CP
2K
Q
6 12 K
Q
7
CD
CD
15
VCC = PIN 16 14
GND = PIN 8
FACT DATA
5-1
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