XC2285 データシートの表示（PDF） - Infineon Technologies

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XC2285

16/32-Bit Single-Chip Microcontroller with 32-Bit Performance

Infineon Technologies 

XC2287 / XC2286 / XC2285

XC2000 Family Derivatives

Preliminary

Electrical Parameters

Variable Memory Cycles

External bus cycles of the XC228x are executed in five subsequent cycle phases (AB,

C, D, E, F). The duration of each cycle phase is programmable (via the TCONCSx

registers) to adapt the external bus cycles to the respective external module (memory,

peripheral, etc.).

The duration of the access phase can optionally be controlled by the external module via

the READY handshake input.

This table provides a summary of the phases and the respective choices for their

duration.

Table 21 Programmable Bus Cycle Phases (see timing diagrams)

Bus Cycle Phase

Parameter Valid Values Unit

Address setup phase, the standard duration of this tpAB

phase (1 … 2 TCS) can be extended by 0 … 3 TCS

if the address window is changed

1 … 2 (5) TCS

Command delay phase

tpC

0…3

TCS

Write Data setup/MUX Tristate phase

tpD

0…1

TCS

Access phase

tpE

1 … 32

TCS

Address/Write Data hold phase

tpF

0…3

TCS

Note: The bandwidth of a parameter (minimum and maximum value) covers the whole

operating range (temperature, voltage) as well as process variations. Within a

given device, however, this bandwidth is smaller than the specified range. This is

also due to interdependencies between certain parameters. Some of these

interdependencies are described in additional notes (see standard timing).

Timing values are listed in Table 22 and Table 23. The shaded parameters have been

verified by characterization. They are not subject to production test.

Data Sheet

94

V0.91, 2007-02

Draft Version

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