LE82Q965SLJAC データシートの表示（PDF） - Intel
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LE82Q965SLJAC Datasheet PDF : 402 Pages
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3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.10
3.11
3.2.2
3.2.3
TSEG ..................................................................................... 58
Pre-allocated Memory ..............................................................58
PCI Memory Address Range (TOLUD – 4 GB) ............................................59
3.3.1
3.3.2
3.3.3
3.3.4
APIC Configuration Space (FEC0_0000h–FECF_FFFFh) ..................60
HSEG (FEDA_0000h–FEDB_FFFFh).............................................60
FSB Interrupt Memory Space (FEE0_0000–FEEF_FFFF) ................. 60
High BIOS Area.......................................................................61
Main Memory Address Space (4 GB to TOUUD) .........................................61
3.4.1 Memory Re-claim Background ...................................................62
3.4.2 Memory Reclaiming .................................................................62
PCI Express* Configuration Address Space (Intel® 82Q965, 82G965, 82P965
(G)MCH Only) ......................................................................................62
PCI Express* Graphics Attach (PEG) (Intel® 82Q965, 82G965, 82P965 (G)MCH
Only) .................................................................................................. 63
Graphics Memory Address Ranges (Intel® 82Q965, 82Q963, 82G965 GMCH
Only) .................................................................................................. 64
System Management Mode (SMM) ..........................................................64
3.8.1
3.8.2
3.8.3
3.8.4
3.8.5
3.8.6
3.8.7
SMM Space Definition ..............................................................65
SMM Space Restrictions............................................................65
SMM Space Combinations .........................................................66
SMM Control Combinations .......................................................66
SMM Space Decode and Transaction Handling..............................67
Processor WB Transaction to an Enabled SMM Address Space ........67
SMM Access Through GTT TLB (Intel® 82Q965, 82Q963, 82G965
GMCH Only) ...........................................................................67
Memory Shadowing ..............................................................................68
I/O Address Space................................................................................68
3.10.1 PCI Express* I/O Address Mapping (Intel® 82Q965, 82G965, 82P965
(G)MCH Only) .........................................................................69
(G)MCH Decode Rules and Cross-Bridge Address Mapping ..........................69
3.11.1 Legacy VGA and I/O Range Decode Rules ...................................70
4
(G)MCH Register Description ............................................................................71
4.1 Register Terminology ............................................................................72
4.2 Configuration Process and Registers ........................................................73
4.2.1 Platform Configuration Structure ...............................................73
4.3 Configuration Mechanisms .....................................................................74
4.3.1
4.3.2
Standard PCI Configuration Mechanism ......................................74
PCI Express* Enhanced Configuration Mechanism (Intel® 82Q965,
82G965, 82P965 (G)MCH Only) .................................................75
4.4 Routing Configuration Accesses ..............................................................76
4.4.1
4.4.2
Internal Device Configuration Accesses.......................................77
Bridge Related Configuration Accesses........................................78
4.5 I/O Mapped Registers ...........................................................................79
4.5.1
4.5.2
CONFIG_ADDRESS—Configuration Address Register ..................... 79
CONFIG_DATA—Configuration Data Register ............................... 81
5
Host Bridge/DRAM Controller Registers (Device 0, Function 0)...............................83
5.1 Host Bridge/DRAM Controller Configuration Register Details (Device 0,
Function 0)..........................................................................................83
5.1.1 VID—Vendor Identification........................................................85
5.1.2 DID—Device Identification ........................................................85
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