LE82Q965SLJAC データシートの表示（PDF） - Intel

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LE82Q965SLJAC

Intel® 965 Express Chipset Family

Intel 

5.1.3 PCICMD—PCI Command ...........................................................86

5.1.4 PCISTS—PCI Status .................................................................87

5.1.5 RID—Revision Identification ......................................................88

5.1.6 CC—Class Code.......................................................................88

5.1.7 MLT—Master Latency Timer ......................................................89

5.1.8 HDR—Header Type ..................................................................89

5.1.9 SVID—Subsystem Vendor Identification......................................89

5.1.10 SID—Subsystem Identification ..................................................90

5.1.11 CAPPTR—Capabilities Pointer ....................................................90

5.1.12 PXPEPBAR—PCI Express* Egress Port Base Address (Intel®

82Q965/82G965/82P965 (G)MCH Only)......................................91

5.1.13 MCHBAR—(G)MCH Memory-Mapped Register Range Base..............92

5.1.14 GGC—GMCH Graphics Control Register (Intel® 82Q965, 82Q963,

82G965 GMCH Only)................................................................93

5.1.15 DEVEN—Device Enable.............................................................94

5.1.16 PCI EXPRESS*XBAR—PCI Express* Register Range Base Address

(Intel® 82Q965, 82G965, 82P965 (G)MCH Only) ..........................95

5.1.17 DMIBAR—Root Complex Register Range Base Address ..................97

5.1.18 PAM0—Programmable Attribute Map 0........................................98

5.1.19 PAM1—Programmable Attribute Map 1........................................99

5.1.20 PAM2—Programmable Attribute Map 2...................................... 100

5.1.21 PAM3—Programmable Attribute Map 3...................................... 101

5.1.22 PAM4—Programmable Attribute Map 4...................................... 102

5.1.23 PAM5—Programmable Attribute Map 5...................................... 103

5.1.24 PAM6—Programmable Attribute Map 6...................................... 104

5.1.25 LAC—Legacy Access Control.................................................... 105

5.1.26 REMAPBASE—Remap Base Address Register.............................. 107

5.1.27 REMAPLIMIT—Remap Limit Address Register ............................. 107

5.1.28 SMRAM—System Management RAM Control .............................. 108

5.1.29 ESMRAMC—Extended System Management RAM Control ............. 109

5.1.30 TOM—Top of Memory............................................................. 110

5.1.31 TOUUD—Top of Upper Usable DRAM......................................... 111

5.1.32 GBSM—Graphics Base of Stolen Memory (Intel® 82G965, 82Q965,

82063Q GMCH Only).............................................................. 111

5.1.33 TSEGMB—TSEG Memory Base ................................................. 112

5.1.34 TOLUD—Top of Low Usable DRAM ............................................ 113

5.1.35 ERRSTS—Error Status ............................................................ 114

5.1.36 ERRCMD—Error Command ...................................................... 115

5.1.37 SMICMD—SMI Command........................................................ 116

5.1.38 SKPD—Scratchpad Data ......................................................... 117

5.1.39 CAPID0—Capability Identifier .................................................. 117

5.2 MCHBAR Registers.............................................................................. 118

5.2.1 CHDECMISC—Channel Decode Miscellaneous............................. 121

5.2.2 C0DRB0—Channel 0 DRAM Rank Boundary Address 0 ................. 122

5.2.3 C0DRB1—Channel 0 DRAM Rank Boundary Address 1 ................. 123

5.2.4 C0DRB2—Channel 0 DRAM Rank Boundary Address 2 ................. 124

5.2.5 C0DRB3—Channel 0 DRAM Rank Boundary Address 3 ................. 124

5.2.6 C0DRA01—Channel 0 DRAM Rank 0,1 Attribute ......................... 125

5.2.7 C0DRA23—Channel 0 DRAM Rank 2,3 Attribute ......................... 126

5.2.8 C0CYCTRKPCHG—Channel 0 CYCTRK Precharge......................... 126

5.2.9 C0CYCTRKACT—Channel 0 CYCTRK ACT ................................... 127

5.2.10 C0CYCTRKWR—Channel 0 CYCTRK WR ..................................... 128

5.2.11 C0CYCTRKRD—Channel 0 CYCTRK READ................................... 128

5.2.12 C0CYCTRKREFR—Channel 0 CYCTRK REFR ................................ 129

5.2.13 C0CKECTRL—Channel 0 CKE Control ........................................ 130

Datasheet

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