MAX5318 データシートの表示（PDF） - Maxim Integrated
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MAX5318 Datasheet PDF : 41 Pages
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MAX5318
18-Bit, High-Accuracy Voltage Output DAC with
Digital Gain, Offset Control, and SPI Interface
DIGITAL INTERFACE ELECTRICAL CHARACTERISTICS
(VAVDD = 5V, VDDIO = 1.8V to 2.7V, VAVSS = -1.25V, VREF = 4.096V, RL = 10kω, TC/SB = M/Z = DGND, CREFO = 100pF, CBYPASS
= 1µF, TA = -40°C to +105°C, unless otherwise noted. Typical values are at TA = +25°C.)(GAIN = 0x3FFFF and OFFSET = 0x00000.)
(Note 2)
PARAMETER
SYMBOL
DIGITAL INPUTS (SCLK, DIN, CS, LDAC, M/Z, RST)
Input High Voltage
VIH
CONDITIONS
MIN TYP MAX UNITS
0.8 x
VDDIO
V
Input Low Voltage
VIL
Input Hysteresis (Note 4)
VIHYST
Input Leakage Current
IIN
Input = 0V at VDDIO
Input Capacitance
CIN
DIGITAL OUTPUTS CHARACTERISTICS (DOUT, READY, BUSY)
Output Low Voltage
VOL
ISOURCE = 1.0mA
Output High Voltage
VOH
ISINK = 1.0mA, except for BUSY
0.2 x
VDDIO
V
200
300
mV
Q0.1 Q1
FA
10
pF
VDDIO
- 0.2
0.2
V
V
Output Three-State Leakage
Output Three-State Capacitance
Output Short-Circuit Current
TIMING CHARACTERISTICS
Serial Clock Frequency
SCLK Period
IOZ
COZ
IOSS
fSCLK
tCP
DOUT only
DOUT only
VDDIO = 2.7V
Stand-alone write mode
Stand-alone read mode and daisy-
chained read and write modes (Note 6)
Stand-alone write mode
Stand-alone read mode and daisy-
chained read and write modes
Q0.1 Q1
15
Q150
50
8
20
125
FA
pF
mA
MHz
ns
SCLK Pulse-Width High
tCH
40% duty cycle
9
ns
SCLK Pulse-Width Low
tCL
40% duty cycle
9
ns
Stand-alone write mode
12
CS Fall to SCLK Fall Setup Time
tCSSO
First SCLK Stand-alone read mode
falling edge and daisy-chained read
72
ns
and write modes
CS Fall to SCLK Fall Hold Time
tCSH0
Inactive falling edge preceding first
falling edge
0
SCLK Fall to CS Rise Hold Time
tCSH1 24th falling edge
4
DIN to SCLK Fall Setup Time
tDS
8
DIN to SCLK Fall Hold Time
tDH
8
SCLK Rise to DOUT Settle Time
tDOT
CL = 20pF (Note 7)
SCLK Rise to DOUT Hold Time
tDOH
CL = 0pF (Note 7)
2
ns
ns
ns
ns
40
ns
ns
Maxim Integrated
9
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