K6R1016C1 データシートの表示（PDF） - Samsung
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K6R1016C1 Datasheet PDF : 11 Pages
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K6R1016C1D
PRELIMINARY
CMOS SRAM
READ CYCLE*
Parameter
Symbol
Min
Read Cycle Time
tRC
10
Address Access Time
tAA
-
Chip Select to Output
tCO
-
Output Enable to Valid Output
tOE
-
UB, LB Access Time
tBA
-
Chip Enable to Low-Z Output
tLZ
3
Output Enable to Low-Z Output
tOLZ
0
UB, LB Enable to Low-Z Output
tBLZ
0
Chip Disable to High-Z Output
tHZ
0
Output Disable to High-Z Output
tOHZ
0
UB, LB Disable to High-Z Output
tBHZ
0
Output Hold from Address Change
tOH
3
Chip Selection to Power Up Time
tPU
0
Chip Selection to Power DownTime tPD
-
* The above parameters are also guaranteed at industrial temperature range.
K6R1016C1D-10
Max
-
10
10
5
5
-
-
-
5
5
5
-
-
10
WRITE CYCLE*
Parameter
Symbol
K6R1016C1D-10
Min
Write Cycle Time
tWC
10
Chip Select to End of Write
tCW
7
Address Set-up Time
tAS
0
Address Valid to End of Write
tAW
7
Write Pulse Width(OE High)
tWP
7
Write Pulse Width(OE Low)
tWP1
10
UB, LB Valid to End of Write
tBW
7
Write Recovery Time
tWR
0
Write to Output High-Z
tWHZ
0
Data to Write Time Overlap
tDW
5
Data Hold from Write Time
tDH
0
End of Write to Output Low-Z
tOW
3
* The above parameters are also guaranteed at industrial temperature range.
Max
-
-
-
-
-
-
-
-
5
-
-
-
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL
Address
Data Out
tRC
tOH
tAA
Previous Valid Data
Valid Data
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-6-
Rev. 3.0
July 2004
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