CY7C1061AV33 データシートの表示（PDF） - Cypress Semiconductor

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CY7C1061AV33

16-Mbit (1 M × 16) Static RAM

Cypress Semiconductor 

CY7C1061AV33

Switching Waveforms

Figure 5. Read Cycle No. 1 (Address Transition Controlled) [14, 15]

tRRCC

ADDRESS

tAA

tOHA

DATA OUT

PREVIOUS DATA VALID

DATA VALID

ADDRESS

CE1

CE2

BHE/BLE

OE

DATA OUT

VCC

SUPPLY

CURRENT

Figure 6. Read Cycle No. 2 (OE Controlled) [15, 16]

tRC

tACE

tLZBE

tDBE

tDOE

tLZOE

HIGH IMPEDANCE

tLZCE

tPU

50%

tPD

tHZCE

tHZBE

tHZOE

DATA VALID

HIGH

IMPEDANCE

ICC

50%

ISB

Notes

14. Device is continuously selected. OE, CE, BHE or BHE, or both = VIL. CE2 = VIH.

15. WE is HIGH for Read cycle.

16. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.

Document Number: 38-05256 Rev. *L

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