CY7C1061AV33 データシートの表示（PDF） - Cypress Semiconductor

部品番号

コンポーネント説明

メーカー

CY7C1061AV33

16-Mbit (1 M × 16) Static RAM

Cypress Semiconductor 

CY7C1061AV33

Switching Waveforms (continued)

Figure 7. Write Cycle No. 1 (CE1 or CE2 Controlled) [17, 18]

tWC

ADDRESS

CE1

tSCE

CE2

WE

tSA

tAW

tHA

tPWE

BHE/BLE

tBW

OE

DATA IO

ADDRESS

CE1

NOTE 19

tSD

tHD

VALID DATA

tHZOE

Figure 8. Write Cycle No. 2 (WE Controlled, OE LOW) [17, 18, 20]

tWC

tSCE

CE2

BHE/BLE

tSA

WE

tBW

tAW

tPWE

DATA IO

NOTE 19

tSD

VALID DATA

tHZWE

Notes

17. Data IO is high impedance if OE, or BHE or BLE or both = VIH.

18. If CE1 goes HIGH simultaneously with WE going HIGH, the output remains in a high impedance state.

19. During this period, the IOs are in output state and input signals should not be applied.

20. The minimum Write cycle time for Write Cycle No. 2 (WE controlled, OE LOW) is the sum of tHZWE and tSD.

Document Number: 38-05256 Rev. *L

tHA

tHD

tLZWE

Page 9 of 17

Share Link: