74LVTH273SJX データシートの表示（PDF） - Fairchild Semiconductor

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74LVTH273SJX

Low Voltage Octal D-Type Flip-Flop with Clear

Fairchild Semiconductor 

Connection Diagram

Pin Descriptions

Pin Names

D0–D7

CP

CLR

O0–O7

Truth Table

Description

Data Inputs

Clock Pulse Input

Clear

Outputs

Inputs

Outputs

Dn

H

L

CP



CLR

H

H

On

H

L

X

H or L

H

Oo

X

X

L

L

H HIGH Voltage Level

L LOW Voltage Level

X Immaterial

LOW-to-HIGH Transition

Oo Previous Oo before HIGH-to-LOW of CP

Functional Description

The LVTH273 consists of eight positive-edge-triggered flip-flops with individual D-type inputs. The buffered Clock and Clear

are common to all flip-flops. The eight flip-flops will store the state of their individual D-type inputs that meet the setup and

hold time requirements on the LOW-to-HIGH Clock (CP) transition. When the Clock is either HIGH or LOW, the D-input sig-

nal has no effect at the output. When the Clear (CLR) is LOW, all Outputs will be forced LOW.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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