74ACT825CW データシートの表示（PDF） - Fairchild Semiconductor
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74ACT825CW Datasheet PDF : 7 Pages
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Functional Description
The ACT825 consists of eight D-type edge-triggered flip-
flops. These devices have 3-STATE outputs for bus sys-
tems, organized in a broadside pinning. In addition to the
clock and output enable pins, the buffered clock (CP) and
buffered Output Enable (OE) are common to all flip-flops.
The flip-flops will store the state of their individual D inputs
that meet the setup and hold time requirements on the
LOW-to-HIGH CP transition. With OE1, OE2 and OE3
LOW, the contents of the flip-flops are available at the out-
puts. When one of OE1, OE2 or OE3 is HIGH, the outputs
go to the high impedance state.
Function Table
Operation of the OE input does not affect the state of the
flip-flops. The ACT825 has Clear (CLR) and Clock Enable
(EN) pins. These pins are ideal for parity bus interfacing in
high performance systems.
When CLR is LOW and OE is LOW, the outputs are LOW.
When CLR is HIGH, data can be entered into the flip-flops.
When EN is LOW, data on the inputs is transferred to the
outputs on the LOW-to-HIGH clock transition. When EN is
HIGH, the outputs do not change state, regardless of the
data or clock input transitions.
Inputs
OE
H
CLR
X
EN
L
CP
Dn
L
H
X
L
H
H
L
X
X
X
L
L
X
X
X
H
H
H
X
X
L
H
H
H
H
H
L
H
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
= LOW-to-HIGH Transition
NC = No Change
H
L
X
X
L
L
H
L
L
L
H
Logic Diagram
Internal
Q
L
H
L
L
NC
NC
L
H
L
H
Output
O
Z
Z
Z
L
Z
NC
Z
Z
L
H
Function
High-Z
High-Z
Clear
Clear
Hold
Hold
Load
Load
Load
Load
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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