74ABT652 データシートの表示（PDF） - Fairchild Semiconductor

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74ABT652

Octal Transceivers and Registers with 3-STATE Outputs

Fairchild Semiconductor 

Truth Table

Inputs

Inputs/Outputs (Note 1)

Operating Mode

OEAB OEBA CPAB CPBA SAB SBA A0 thru A7 B0 thru B7

L

L

X

H

L

L

H

H

H

H

X

L

H or L H or L

 H or L

  H or L

X

X

X

X

X

X

X Input

Input

Isolation

X

Store A and B Data

X Input

Not Specified Store A, Hold B

X Input

Output

Store A in Both Registers

X Not Specified Input

Hold A, Store B

X Output

Input

Store B in Both Registers

L

L

X

X

X

L Output

Input

Real-Time B Data to A Bus

L

L

X H or L X

H

Store B Data to A Bus

H

H

X

X

L

X Input

Output

Real-Time A Data to B Bus

H

H H or L X

H

X

Stored A Data to B Bus

H

L H or L H or L H

H Output

Output

Stored A Data to B Bus and

Stored B Data to A Bus

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

= LOW to HIGH Clock Transition

Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e.,

data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs.

Functional Description

In the transceiver mode, data present at the HIGH imped-

ance port may be stored in either the A or B register or

both.

The select (SAB, SBA) controls can multiplex stored and

real-time.

The examples in Figure 1 demonstrate the four fundamen-

tal bus-management functions that can be performed with

the ABT652.

Data on the A or B data bus, or both, can be stored in the

internal D flip-flop by LOW to HIGH transitions at the

appropriate Clock Inputs (CPAB, CPBA) regardless of the

Select or Output Enable Inputs. When SAB and SBA are in

the real time transfer mode, it is also possible to store data

without using the internal D flip-flops by simultaneously

enabling OEAB and OEBA. In this configuration each Out-

put reinforces its Input. Thus when all other data sources to

the two sets of bus lines are in a HIGH impedance state,

each set of bus lines will remain at its last state.

Logic Diagram

Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.

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